VLSI models of network-on-chip interconnect

Dimitrios N. Serpanos, Wayne Wolf

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

We use VLSI circuit models to analyze the relative delay of interconnect subsystems for networks-on-chips (NoCs). Most work in NoCs has selected a network topology based on higher-level performance models, such as packet delay. Our model parameterizes the interconnect subsystem size by N, the number of IP cores (processors, memories, etc.) to be connected. This paper analyzes busses, crossbars, and some multi-stage networks. We compare the delay required transfer a specific amount of information (bits) between two cores. Considering the data transfer parallelism in crossbars, we make 2 different comparisons: (i) transfer between 2 devices, and (ii) parallel transfers between all devices.

Original languageEnglish
Title of host publication2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
Pages72-77
Number of pages6
DOIs
Publication statusPublished - 1 Dec 2007
Event2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC - Atlanta, GA, United States
Duration: 15 Oct 200717 Oct 2007

Publication series

Name2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC

Other

Other2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
CountryUnited States
CityAtlanta, GA
Period15/10/0717/10/07

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Serpanos, D. N., & Wolf, W. (2007). VLSI models of network-on-chip interconnect. In 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC (pp. 72-77). [4402475] (2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC). https://doi.org/10.1109/VLSISOC.2007.4402475