VLSI implementation of a binary neural network-two case studies

Amine Bermak, J. Austin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The bit-level architecture consists of an n×m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters. Since we are interested in the VLSI implementation of such networks, hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.

Original languageEnglish
Title of host publicationProceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages374-379
Number of pages6
ISBN (Electronic)0769500439, 9780769500430
DOIs
Publication statusPublished - 1 Jan 1999
Event7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999 - Granada, Spain
Duration: 7 Apr 19999 Apr 1999

Other

Other7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999
CountrySpain
CityGranada
Period7/4/999/4/99

Fingerprint

Neural networks
Data storage equipment
Motor Vehicles
Memory architecture
Adders
Random access storage
Hardware

Keywords

  • Binary neural networks
  • Bit-level architecture
  • Internal storage processors
  • VLSI implementation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Signal Processing
  • Neuroscience (miscellaneous)
  • Electrical and Electronic Engineering

Cite this

Bermak, A., & Austin, J. (1999). VLSI implementation of a binary neural network-two case studies. In Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999 (pp. 374-379). [758889] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MN.1999.758889

VLSI implementation of a binary neural network-two case studies. / Bermak, Amine; Austin, J.

Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 374-379 758889.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bermak, A & Austin, J 1999, VLSI implementation of a binary neural network-two case studies. in Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999., 758889, Institute of Electrical and Electronics Engineers Inc., pp. 374-379, 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999, Granada, Spain, 7/4/99. https://doi.org/10.1109/MN.1999.758889
Bermak A, Austin J. VLSI implementation of a binary neural network-two case studies. In Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999. Institute of Electrical and Electronics Engineers Inc. 1999. p. 374-379. 758889 https://doi.org/10.1109/MN.1999.758889
Bermak, Amine ; Austin, J. / VLSI implementation of a binary neural network-two case studies. Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 374-379
@inproceedings{d545fa0f75a2494cbb99fab141e39ce4,
title = "VLSI implementation of a binary neural network-two case studies",
abstract = "A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The bit-level architecture consists of an n×m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters. Since we are interested in the VLSI implementation of such networks, hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.",
keywords = "Binary neural networks, Bit-level architecture, Internal storage processors, VLSI implementation",
author = "Amine Bermak and J. Austin",
year = "1999",
month = "1",
day = "1",
doi = "10.1109/MN.1999.758889",
language = "English",
pages = "374--379",
booktitle = "Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - VLSI implementation of a binary neural network-two case studies

AU - Bermak, Amine

AU - Austin, J.

PY - 1999/1/1

Y1 - 1999/1/1

N2 - A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The bit-level architecture consists of an n×m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters. Since we are interested in the VLSI implementation of such networks, hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.

AB - A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The bit-level architecture consists of an n×m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters. Since we are interested in the VLSI implementation of such networks, hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.

KW - Binary neural networks

KW - Bit-level architecture

KW - Internal storage processors

KW - VLSI implementation

UR - http://www.scopus.com/inward/record.url?scp=78049232371&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78049232371&partnerID=8YFLogxK

U2 - 10.1109/MN.1999.758889

DO - 10.1109/MN.1999.758889

M3 - Conference contribution

SP - 374

EP - 379

BT - Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999

PB - Institute of Electrical and Electronics Engineers Inc.

ER -