Vertical dimensioning: A novel DRR implementation for efficient fair queueing

Spiridon Bakiras, Feng Wang, Dimitris Papadias, Mounir Hamdi

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Fair bandwidth allocation is an important mechanism for traffic management in the Internet. Round robin schedulers, such as Deficit Round Robin (DRR), are well-suited for implementing fair queueing in multi-Gbps routers, as they schedule packets in constant time regardless of the total number of active flows. The main drawback of these schemes, however, lies in the maintenance of per flow queues, which complicates the buffer management module and limits the sharing of the buffer space among the competing flows. In this paper, we introduce a novel packet scheduling mechanism, called Vertical Dimensioning (VD) that modifies the original DRR algorithm to operate without per flow queueing. In particular, VD is based on an array of FIFO buffers, whose size is constant and independent of the total number of active flows. Our results, both analytical and experimental, demonstrate that VD exhibits very good fairness and delay properties that are comparable to the ideal Weighted Fair Queueing (WFQ) scheduler. Furthermore, our scheduling algorithm is shown to outperform significantly existing round robin schedulers when the amount of buffering at the router is small.

Original languageEnglish
Pages (from-to)3476-3484
Number of pages9
JournalComputer Communications
Volume31
Issue number14
DOIs
Publication statusPublished - 5 Sep 2008

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Keywords

  • Deficit round robin
  • Fair queueing
  • Packet scheduling

ASJC Scopus subject areas

  • Computer Networks and Communications

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