Two-stage interface circuit design for a 32-color resolution optical sensor

Maher Assaad, Israel Yohannes, Amine Bermak

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage.

Original languageEnglish
Article number6329923
Pages (from-to)610-617
Number of pages8
JournalIEEE Sensors Journal
Volume13
Issue number2
DOIs
Publication statusPublished - 2013
Externally publishedYes

Fingerprint

Optical sensors
optical measuring instruments
Color
color
polychlorinated biphenyls
Networks (circuits)
Polychlorinated biphenyls
Electric power utilization
chips
shelves
high resolution
Electric potential
electric potential
simulation

Keywords

  • Interface circuit
  • mixed signal
  • optical sensor

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Two-stage interface circuit design for a 32-color resolution optical sensor. / Assaad, Maher; Yohannes, Israel; Bermak, Amine.

In: IEEE Sensors Journal, Vol. 13, No. 2, 6329923, 2013, p. 610-617.

Research output: Contribution to journalArticle

Assaad, Maher ; Yohannes, Israel ; Bermak, Amine. / Two-stage interface circuit design for a 32-color resolution optical sensor. In: IEEE Sensors Journal. 2013 ; Vol. 13, No. 2. pp. 610-617.
@article{4be70c00db2940ac85cacd3f51086df3,
title = "Two-stage interface circuit design for a 32-color resolution optical sensor",
abstract = "An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage.",
keywords = "Interface circuit, mixed signal, optical sensor",
author = "Maher Assaad and Israel Yohannes and Amine Bermak",
year = "2013",
doi = "10.1109/JSEN.2012.2224331",
language = "English",
volume = "13",
pages = "610--617",
journal = "IEEE Sensors Journal",
issn = "1530-437X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

TY - JOUR

T1 - Two-stage interface circuit design for a 32-color resolution optical sensor

AU - Assaad, Maher

AU - Yohannes, Israel

AU - Bermak, Amine

PY - 2013

Y1 - 2013

N2 - An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage.

AB - An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage.

KW - Interface circuit

KW - mixed signal

KW - optical sensor

UR - http://www.scopus.com/inward/record.url?scp=84872297914&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84872297914&partnerID=8YFLogxK

U2 - 10.1109/JSEN.2012.2224331

DO - 10.1109/JSEN.2012.2224331

M3 - Article

AN - SCOPUS:84872297914

VL - 13

SP - 610

EP - 617

JO - IEEE Sensors Journal

JF - IEEE Sensors Journal

SN - 1530-437X

IS - 2

M1 - 6329923

ER -