Synchronous bus arbitration with constant logic per module

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Abstract

A novel technique for distributed synchronous bus arbitration is presented in this paper. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps)., only the width of the arbitration bus must be increased in this case.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherPubl by IEEE
Pages35-41
Number of pages7
ISBN (Print)0818656026
Publication statusPublished - 1 Jan 1994
EventProceedings of the 8th International Parallel Processing Symposium - Cancun, Mex
Duration: 26 Apr 199429 Apr 1994

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Other

OtherProceedings of the 8th International Parallel Processing Symposium
CityCancun, Mex
Period26/4/9429/4/94

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ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Alnuweiri, H. M. (1994). Synchronous bus arbitration with constant logic per module. In Proceedings of the International Conference on Parallel Processing (pp. 35-41). (Proceedings of the International Conference on Parallel Processing). Publ by IEEE.