Scalable memory management for ATM systems

D. N. Serpanos, P. Karakonstantis

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The scalability of SDH/SONET to high speeds places strict performance requirements on ATM systems. Throughput preservation of link speed through protocols to a higher layer application is a known problem in high-speed communication systems, which becomes more acute as link speed increases and is being addressed with designs that offer high speed data paths and high embedded processing power. We introduce a specialized, high-speed, scalable and reusable Queue Manager (QM) for ATM systems, which enables high-speed data transfer to/from system memory and management of logical data structures. We describe its architecture, and then we present implementations in hardware as well as in software for embedded systems. We evaluate the implementations, demonstrating the performance improvement and the system scalability.

Original languageEnglish
Title of host publicationIEEE Symposium on Computers and Communications - Proceedings
Pages385-390
Number of pages6
Publication statusPublished - 1 Jan 2000
Externally publishedYes
EventISCC 2000 - 5th IEEE Symposium on Computers and Communications -
Duration: 3 Jul 20006 Jul 2000

Other

OtherISCC 2000 - 5th IEEE Symposium on Computers and Communications
Period3/7/006/7/00

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ASJC Scopus subject areas

  • Computer Science(all)
  • Engineering(all)

Cite this

Serpanos, D. N., & Karakonstantis, P. (2000). Scalable memory management for ATM systems. In IEEE Symposium on Computers and Communications - Proceedings (pp. 385-390)