### Abstract

A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. This paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N^{2}/Q^{2}) area, and O(wQ) time, where w is the word length of the permuted elements and 1≤Q≤√N/w.

Original language | English |
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Title of host publication | Proceedings of the International Conference on Parallel Processing |

Publisher | Publ by IEEE |

Pages | 116-119 |

Number of pages | 4 |

ISBN (Print) | 0818626720 |

Publication status | Published - 1 Dec 1992 |

Externally published | Yes |

Event | Proceedings of the 6th International Parallel Processing Symposium - Beverly Hills, CA, USA Duration: 23 Mar 1992 → 26 Mar 1992 |

### Other

Other | Proceedings of the 6th International Parallel Processing Symposium |
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City | Beverly Hills, CA, USA |

Period | 23/3/92 → 26/3/92 |

### Fingerprint

### ASJC Scopus subject areas

- Hardware and Architecture

### Cite this

*Proceedings of the International Conference on Parallel Processing*(pp. 116-119). Publ by IEEE.

**Routing BPC permutations in VLSI.** / Alnuweiri, Hussein.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings of the International Conference on Parallel Processing.*Publ by IEEE, pp. 116-119, Proceedings of the 6th International Parallel Processing Symposium, Beverly Hills, CA, USA, 23/3/92.

}

TY - GEN

T1 - Routing BPC permutations in VLSI

AU - Alnuweiri, Hussein

PY - 1992/12/1

Y1 - 1992/12/1

N2 - A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. This paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N2/Q2) area, and O(wQ) time, where w is the word length of the permuted elements and 1≤Q≤√N/w.

AB - A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. This paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N2/Q2) area, and O(wQ) time, where w is the word length of the permuted elements and 1≤Q≤√N/w.

UR - http://www.scopus.com/inward/record.url?scp=0026962464&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026962464&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026962464

SN - 0818626720

SP - 116

EP - 119

BT - Proceedings of the International Conference on Parallel Processing

PB - Publ by IEEE

ER -