Routing BPC permutations in VLSI

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. This paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N2/Q2) area, and O(wQ) time, where w is the word length of the permuted elements and 1≤Q≤√N/w.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherPubl by IEEE
Pages116-119
Number of pages4
ISBN (Print)0818626720
Publication statusPublished - 1 Dec 1992
Externally publishedYes
EventProceedings of the 6th International Parallel Processing Symposium - Beverly Hills, CA, USA
Duration: 23 Mar 199226 Mar 1992

Other

OtherProceedings of the 6th International Parallel Processing Symposium
CityBeverly Hills, CA, USA
Period23/3/9226/3/92

Fingerprint

Digital arithmetic
Interconnection networks (circuit switching)
Parallel processing systems
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Alnuweiri, H. (1992). Routing BPC permutations in VLSI. In Proceedings of the International Conference on Parallel Processing (pp. 116-119). Publ by IEEE.

Routing BPC permutations in VLSI. / Alnuweiri, Hussein.

Proceedings of the International Conference on Parallel Processing. Publ by IEEE, 1992. p. 116-119.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Alnuweiri, H 1992, Routing BPC permutations in VLSI. in Proceedings of the International Conference on Parallel Processing. Publ by IEEE, pp. 116-119, Proceedings of the 6th International Parallel Processing Symposium, Beverly Hills, CA, USA, 23/3/92.
Alnuweiri H. Routing BPC permutations in VLSI. In Proceedings of the International Conference on Parallel Processing. Publ by IEEE. 1992. p. 116-119
Alnuweiri, Hussein. / Routing BPC permutations in VLSI. Proceedings of the International Conference on Parallel Processing. Publ by IEEE, 1992. pp. 116-119
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