Robust SRAM design via joint sizing and voltage optimization under dynamic stability constraints

Akshit Dayal, Peng Li, Garng Morton Huang

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

Technology scaling has rendered the robust design of SRAMs very challenging due to the escalating process variability. In this paper, we present a yield-aware SRAM optimization approach, wherein, the dominant effect of random process variations, are taken into account in the optimization flow by extracting statistical performance models for stability, access time and leakage power. More importantly, in addition to transistor sizing, we show that optimizing the Supply voltage and Wordline voltage provides important, extra design freedom and leads to improved cell designs. Furthermore, it is shown that it is critical to precisely characterize SRAM stability from a dynamical point of view with shrinking access cycle time. The use of such dynamic noise margins in the design flow avoids overdesign and failures in meeting dynamic constraints which could be resulted otherwise when traditional static noise margins are employed.

Original languageEnglish
Pages (from-to)66-79
Number of pages14
JournalJournal of Low Power Electronics
Volume6
Issue number1
DOIs
Publication statusPublished - 1 Apr 2010
Externally publishedYes

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Static random access storage
Electric potential
Random processes
Transistors

Keywords

  • Access time
  • Dynamic noise margin
  • Leakage power
  • Nonlinear optimization
  • Static noise margin

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Robust SRAM design via joint sizing and voltage optimization under dynamic stability constraints. / Dayal, Akshit; Li, Peng; Huang, Garng Morton.

In: Journal of Low Power Electronics, Vol. 6, No. 1, 01.04.2010, p. 66-79.

Research output: Contribution to journalArticle

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