Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique

Saqib Mohamad, Moaaz Ahmed, Jie Yuan, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Incremental analog to digital converters (IADCs) are aimed at converting low frequency signals with high accuracy. The operational transconductance amplifiers (OTAs) used to implement the integrators are the dominant source of power consumption, since they must settle to a desired accuracy within a given clock period, by driving a capacitive load. Reducing the capacitor size correspondingly increases the thermal noise power which reduces the signal-to-noise ratio (SNR) of the ADC. In this paper, we introduce a capacitor scaling technique which exploits the uneven weightage of the IADC decimation filter on the output bit-stream of the IADC. The power consumption can be scaled down correspondingly but the noise power does not increase by the same extent, leading to greater energy efficiency. A second order feedforward IADC is simulated to demonstrate the idea, which achieves up to a 25% improvement in energy efficiency using the proposed scheme.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2018-May
ISBN (Electronic)9781538648810
DOIs
Publication statusPublished - 26 Apr 2018
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 27 May 201830 May 2018

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period27/5/1830/5/18

Fingerprint

Digital to analog conversion
Capacitors
Energy efficiency
Electric power utilization
Thermal noise
Operational amplifiers
Clocks
Signal to noise ratio

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Mohamad, S., Ahmed, M., Yuan, J., & Bermak, A. (2018). Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings (Vol. 2018-May). [8351289] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351289

Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique. / Mohamad, Saqib; Ahmed, Moaaz; Yuan, Jie; Bermak, Amine.

2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Vol. 2018-May Institute of Electrical and Electronics Engineers Inc., 2018. 8351289.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mohamad, S, Ahmed, M, Yuan, J & Bermak, A 2018, Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. vol. 2018-May, 8351289, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/5/18. https://doi.org/10.1109/ISCAS.2018.8351289
Mohamad S, Ahmed M, Yuan J, Bermak A. Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Vol. 2018-May. Institute of Electrical and Electronics Engineers Inc. 2018. 8351289 https://doi.org/10.1109/ISCAS.2018.8351289
Mohamad, Saqib ; Ahmed, Moaaz ; Yuan, Jie ; Bermak, Amine. / Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Vol. 2018-May Institute of Electrical and Electronics Engineers Inc., 2018.
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