Power optimization in multipliers using multi-precision combined with voltage scaling techniques

Xiaoxiao Zhang, Amine Bermak, Farid Boussaid

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Low-power design is essential for computationintensive systems such as Digital Signal Processors (DSP) as well as battery-powered devices. This paper presents a novel low-power multiplier architecture, which exploits the effective dynamic range of the input data and performs a run-time multi-precision multiplication. Block-wise shutdown and voltage scaling techniques are combined to disable unused resources and adjust the supply voltage and clock frequency to reduce power consumption. This results in nearly a cubic reduction in dynamic power dissipation. Furthermore, by using modified Booth encoding scheme, partial products generating algorithm, and compression topology, our multiplier achieves both delay and power reduction. The design is synthesized using TSMC 0:18μm standard cell library and evaluated in Synopsys design environment. Reported results show that our multiplier achieves up to 75% power reduction with less than 10% overhead in terms of silicon area.

Original languageEnglish
Title of host publication2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009
Pages79-82
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009 - Kuala Lumpur, Malaysia
Duration: 15 Jul 200916 Jul 2009

Other

Other2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009
CountryMalaysia
CityKuala Lumpur
Period15/7/0916/7/09

Fingerprint

Digital signal processors
Clocks
Energy dissipation
Electric power utilization
Topology
Silicon
Electric potential
Voltage scaling

Keywords

  • Low-power
  • Multi-precision
  • Multiplier
  • Voltage scaling

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Zhang, X., Bermak, A., & Boussaid, F. (2009). Power optimization in multipliers using multi-precision combined with voltage scaling techniques. In 2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009 (pp. 79-82). [5206295] https://doi.org/10.1109/ASQED.2009.5206295

Power optimization in multipliers using multi-precision combined with voltage scaling techniques. / Zhang, Xiaoxiao; Bermak, Amine; Boussaid, Farid.

2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009. 2009. p. 79-82 5206295.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, X, Bermak, A & Boussaid, F 2009, Power optimization in multipliers using multi-precision combined with voltage scaling techniques. in 2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009., 5206295, pp. 79-82, 2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009, Kuala Lumpur, Malaysia, 15/7/09. https://doi.org/10.1109/ASQED.2009.5206295
Zhang X, Bermak A, Boussaid F. Power optimization in multipliers using multi-precision combined with voltage scaling techniques. In 2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009. 2009. p. 79-82. 5206295 https://doi.org/10.1109/ASQED.2009.5206295
Zhang, Xiaoxiao ; Bermak, Amine ; Boussaid, Farid. / Power optimization in multipliers using multi-precision combined with voltage scaling techniques. 2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009. 2009. pp. 79-82
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