Phase locked loop with fast tracking over wide stability range under grid faults

Ahmed S. Morsy, Prasad Enjeti, Shehab Ahmed, Ahmed Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper introduces a PLL characterized by fast dynamics, wide stability range and minimal deviations. The proposed PLL is based on a frequency adaptive filtering stage to minimize the frequency and phase deviations under unbalanced conditions and harmonic distortions. Furthermore, a simple mathematical formula is introduced to modify the conventional synchronous frame based PLL to provide more stabilization points for the PLL. The advantages of the proposed PLL are verified through simulations.

Original languageEnglish
Title of host publicationAPEC 2014 - 29th Annual IEEE Applied Power Electronics Conference and Exposition
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1263-1267
Number of pages5
ISBN (Print)9781479923250
DOIs
Publication statusPublished - 2014
Event29th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2014 - Fort Worth, TX, United States
Duration: 16 Mar 201420 Mar 2014

Other

Other29th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2014
CountryUnited States
CityFort Worth, TX
Period16/3/1420/3/14

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Morsy, A. S., Enjeti, P., Ahmed, S., & Massoud, A. (2014). Phase locked loop with fast tracking over wide stability range under grid faults. In APEC 2014 - 29th Annual IEEE Applied Power Electronics Conference and Exposition (pp. 1263-1267). [6803468] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APEC.2014.6803468