Performance enhanced voltage scaling in FPGAs

S. Chandrasekaran, A. Amira, Amine Bermak, M. Shi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

As Field Programmable Gate Array (FPGA) based systems scale up in complexity, energy aware designs paradigms with strict power budgets require the designer to explore all viable options for minimising dynamic power consumption. The concepts of parallelism and pipelining have long been exploited in CMOS chips to reduce power and energy consumption. In this paper, a systematic empirical study of the tradeoffs between degree of parallelism, threshold voltage and power consumption under constant throughput conditions commercially available FPGAs has been presented. Results indicate that there is excellent scope for reduction in dynamic voltage by suitably applying the tradeoffs in FPGA based designs in order to achieve energy efficient implementations.

Original languageEnglish
Title of host publication2007 International Symposium on Integrated Circuits, ISIC
Pages477-480
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 International Symposium on Integrated Circuits, ISIC - Singapore, Singapore
Duration: 26 Sep 200728 Sep 2007

Other

Other2007 International Symposium on Integrated Circuits, ISIC
CountrySingapore
CitySingapore
Period26/9/0728/9/07

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chandrasekaran, S., Amira, A., Bermak, A., & Shi, M. (2007). Performance enhanced voltage scaling in FPGAs. In 2007 International Symposium on Integrated Circuits, ISIC (pp. 477-480). [4441902] https://doi.org/10.1109/ISICIR.2007.4441902