### Abstract

This short note presents constant-time algorithms for label- ing the connected components of an image on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an N x N image in 0(1) time using N2processors, which is optimal. Furthermore, the proposed techniques lead to an O(log N/log log N)-time image labeling algorithm on a network of N2 processors with a reconfigurable bus of width log N bits. It is shown that these techniques can be applied to labeling an undirected N-vertex graph represented by an adjacency matrix.

Original language | English |
---|---|

Pages (from-to) | 105-110 |

Number of pages | 6 |

Journal | IEEE Transactions on Parallel and Distributed Systems |

Volume | 6 |

Issue number | 1 |

DOIs | |

Publication status | Published - 1 Jan 1995 |

Externally published | Yes |

### Fingerprint

### Keywords

- array processing
- constant-time algorithms
- constant-weight codes
- graphs
- image computations
- labeling connected components
- parallel processing
- Reconfigurable networks of processors

### ASJC Scopus subject areas

- Signal Processing
- Hardware and Architecture
- Computational Theory and Mathematics

### Cite this

**Parallel Constant-Time Connectivity Algorithms on a Reconfigurable Network of Processors.** / Alnuweiri, Hussein.

Research output: Contribution to journal › Article

}

TY - JOUR

T1 - Parallel Constant-Time Connectivity Algorithms on a Reconfigurable Network of Processors

AU - Alnuweiri, Hussein

PY - 1995/1/1

Y1 - 1995/1/1

N2 - This short note presents constant-time algorithms for label- ing the connected components of an image on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an N x N image in 0(1) time using N2processors, which is optimal. Furthermore, the proposed techniques lead to an O(log N/log log N)-time image labeling algorithm on a network of N2 processors with a reconfigurable bus of width log N bits. It is shown that these techniques can be applied to labeling an undirected N-vertex graph represented by an adjacency matrix.

AB - This short note presents constant-time algorithms for label- ing the connected components of an image on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an N x N image in 0(1) time using N2processors, which is optimal. Furthermore, the proposed techniques lead to an O(log N/log log N)-time image labeling algorithm on a network of N2 processors with a reconfigurable bus of width log N bits. It is shown that these techniques can be applied to labeling an undirected N-vertex graph represented by an adjacency matrix.

KW - array processing

KW - constant-time algorithms

KW - constant-weight codes

KW - graphs

KW - image computations

KW - labeling connected components

KW - parallel processing

KW - Reconfigurable networks of processors

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U2 - 10.1109/71.363405

DO - 10.1109/71.363405

M3 - Article

AN - SCOPUS:0029229905

VL - 6

SP - 105

EP - 110

JO - IEEE Transactions on Parallel and Distributed Systems

JF - IEEE Transactions on Parallel and Distributed Systems

SN - 1045-9219

IS - 1

ER -