Multistep ADC family with efficient architecture

Sing Chin, Michael K. Mayes, Raymond Filippi

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A family of 8- and 10-bit A/D (analog/digital) converters has been developed using an efficient multistep architecture. The 10-bit A/D converter requires two 4-bit (two 3-bit for the 8-bit converter) flash cycles and a 3-bit voltage estimator. For the 10-bit converter, the architecture allows a reduction of comparator count to 16 and the resistor count to 96. While the conversion speed is similar to that of conventional half-flash A/D converters, power consumption and die size are lower due to the reduced number of components. The detailed operation of the A/D converter is illustrated, and a summary of test results is given.

Original languageEnglish
Pages (from-to)16-17, 274
JournalUnknown Journal
Volume32
Publication statusPublished - 1989
Externally publishedYes

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chin, S., Mayes, M. K., & Filippi, R. (1989). Multistep ADC family with efficient architecture. Unknown Journal, 32, 16-17, 274.

Multistep ADC family with efficient architecture. / Chin, Sing; Mayes, Michael K.; Filippi, Raymond.

In: Unknown Journal, Vol. 32, 1989, p. 16-17, 274.

Research output: Contribution to journalArticle

Chin, S, Mayes, MK & Filippi, R 1989, 'Multistep ADC family with efficient architecture', Unknown Journal, vol. 32, pp. 16-17, 274.
Chin S, Mayes MK, Filippi R. Multistep ADC family with efficient architecture. Unknown Journal. 1989;32:16-17, 274.
Chin, Sing ; Mayes, Michael K. ; Filippi, Raymond. / Multistep ADC family with efficient architecture. In: Unknown Journal. 1989 ; Vol. 32. pp. 16-17, 274.
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