Abstract
A family of 8- and 10-bit A/D (analog/digital) converters has been developed using an efficient multistep architecture. The 10-bit A/D converter requires two 4-bit (two 3-bit for the 8-bit converter) flash cycles and a 3-bit voltage estimator. For the 10-bit converter, the architecture allows a reduction of comparator count to 16 and the resistor count to 96. While the conversion speed is similar to that of conventional half-flash A/D converters, power consumption and die size are lower due to the reduced number of components. The detailed operation of the A/D converter is illustrated, and a summary of test results is given.
| Original language | English |
|---|---|
| Pages (from-to) | 16-17, 274 |
| Journal | Unknown Journal |
| Volume | 32 |
| Publication status | Published - 1989 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Multistep ADC family with efficient architecture. / Chin, Sing; Mayes, Michael K.; Filippi, Raymond.
In: Unknown Journal, Vol. 32, 1989, p. 16-17, 274.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Multistep ADC family with efficient architecture
AU - Chin, Sing
AU - Mayes, Michael K.
AU - Filippi, Raymond
PY - 1989
Y1 - 1989
N2 - A family of 8- and 10-bit A/D (analog/digital) converters has been developed using an efficient multistep architecture. The 10-bit A/D converter requires two 4-bit (two 3-bit for the 8-bit converter) flash cycles and a 3-bit voltage estimator. For the 10-bit converter, the architecture allows a reduction of comparator count to 16 and the resistor count to 96. While the conversion speed is similar to that of conventional half-flash A/D converters, power consumption and die size are lower due to the reduced number of components. The detailed operation of the A/D converter is illustrated, and a summary of test results is given.
AB - A family of 8- and 10-bit A/D (analog/digital) converters has been developed using an efficient multistep architecture. The 10-bit A/D converter requires two 4-bit (two 3-bit for the 8-bit converter) flash cycles and a 3-bit voltage estimator. For the 10-bit converter, the architecture allows a reduction of comparator count to 16 and the resistor count to 96. While the conversion speed is similar to that of conventional half-flash A/D converters, power consumption and die size are lower due to the reduced number of components. The detailed operation of the A/D converter is illustrated, and a summary of test results is given.
UR - http://www.scopus.com/inward/record.url?scp=0024887001&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0024887001&partnerID=8YFLogxK
M3 - Article
VL - 32
SP - 16-17, 274
JO - JAPCA
JF - JAPCA
SN - 1073-161X
ER -