This paper develops an efficient buffer management scheme that makes generic ATM switches capable of supporting delay-sensitive as well as loss-sensitive traffic. The proposed scheme aims at enhancing the performance of ATM switches by maintaining the head cells of output queues in relatively short dedicated output buffers, while maintaining the long tails of overflowing queues in a shared-memory pool where various memory-space management schemes can be applied. Under this scheme, higher priority (delay-sensitive) cells can be forwarded immediately to the output buffers, where priority-based cell scheduling is exercised. Low-priority (but loss-sensitive) cells are pushed into the shared-memory only if their output buffers are full. If the shared memory is full, then a suitable push-out scheme must be employed to provide fairness. Detailed analysis of the buffer management scheme is provided by decomposing the complex partial sharing buffer analysis into an equivalent queuing problem. Also, extensive simulation is used to elucidate the impact of buffer management policies on the dynamics of interaction among the two traffic classes. The results demonstrate the effectiveness of the proposed scheme in providing each traffic class with the required quality-of-service performance over a wide range of traffic loads and buffer sizes.
|Number of pages||12|
|Journal||International Journal of Parallel and Distributed Systems and Networks|
|Publication status||Published - 1 Dec 1999|
ASJC Scopus subject areas
- Hardware and Architecture