In this paper a real-time mixed analog-digital VLSI implementation of a Shunting Inhibition Cellular Neural Network (SICNN) is presented. Unlike the usual VLSI implementation of vision chips, this circuit is based on a mixed analog-digital technology where the processing is realized using current mode analog approach while the cellular neural network topology (size of the window and connectivity) is realized using a modified digital read-out circuit. A significant processing speed-up is achieved using this technique since the window-based processing of the SICNN is realized in analog-domain while reading the pixel using the modified digital read-out circuit. A prototype including a 58 × 58 pixels and the SICNN processor with a programmable user-defined window size of 3 × 3 or 5 × 5 has been designed. The circuit also includes an amplifier and a successive approximation Analogue-to-digital converter. The circuit has been designed using Alcatel CMOS 0.7 μm technology and occupies a silicon area of 11mm2.
|Number of pages||9|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|Publication status||Published - 1 Dec 2000|
|Event||2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) - Lafayette, LA, USA|
Duration: 11 Oct 2000 → 13 Oct 2000
ASJC Scopus subject areas