Mixed mode real-time VLSI implementation of a shunting inhibition cellular neural network

Amine Bermak, Abdesselam Bouzerdoum

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper a real-time mixed analog-digital VLSI implementation of a Shunting Inhibition Cellular Neural Network (SICNN) is presented. Unlike the usual VLSI implementation of vision chips, this circuit is based on a mixed analog-digital technology where the processing is realized using current mode analog approach while the cellular neural network topology (size of the window and connectivity) is realized using a modified digital read-out circuit. A significant processing speed-up is achieved using this technique since the window-based processing of the SICNN is realized in analog-domain while reading the pixel using the modified digital read-out circuit. A prototype including a 58 × 58 pixels and the SICNN processor with a programmable user-defined window size of 3 × 3 or 5 × 5 has been designed. The circuit also includes an amplifier and a successive approximation Analogue-to-digital converter. The circuit has been designed using Alcatel CMOS 0.7 μm technology and occupies a silicon area of 11mm2.

Original languageEnglish
Pages (from-to)715-723
Number of pages9
JournalIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Publication statusPublished - 2000
Externally publishedYes

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Cellular neural networks
Networks (circuits)
Processing
Pixels
Digital to analog conversion
Topology
Silicon

ASJC Scopus subject areas

  • Engineering(all)

Cite this

@article{ec05c026761d4c2ca59b5b1720a58617,
title = "Mixed mode real-time VLSI implementation of a shunting inhibition cellular neural network",
abstract = "In this paper a real-time mixed analog-digital VLSI implementation of a Shunting Inhibition Cellular Neural Network (SICNN) is presented. Unlike the usual VLSI implementation of vision chips, this circuit is based on a mixed analog-digital technology where the processing is realized using current mode analog approach while the cellular neural network topology (size of the window and connectivity) is realized using a modified digital read-out circuit. A significant processing speed-up is achieved using this technique since the window-based processing of the SICNN is realized in analog-domain while reading the pixel using the modified digital read-out circuit. A prototype including a 58 × 58 pixels and the SICNN processor with a programmable user-defined window size of 3 × 3 or 5 × 5 has been designed. The circuit also includes an amplifier and a successive approximation Analogue-to-digital converter. The circuit has been designed using Alcatel CMOS 0.7 μm technology and occupies a silicon area of 11mm2.",
author = "Amine Bermak and Abdesselam Bouzerdoum",
year = "2000",
language = "English",
pages = "715--723",
journal = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",
issn = "1520-6130",

}

TY - JOUR

T1 - Mixed mode real-time VLSI implementation of a shunting inhibition cellular neural network

AU - Bermak, Amine

AU - Bouzerdoum, Abdesselam

PY - 2000

Y1 - 2000

N2 - In this paper a real-time mixed analog-digital VLSI implementation of a Shunting Inhibition Cellular Neural Network (SICNN) is presented. Unlike the usual VLSI implementation of vision chips, this circuit is based on a mixed analog-digital technology where the processing is realized using current mode analog approach while the cellular neural network topology (size of the window and connectivity) is realized using a modified digital read-out circuit. A significant processing speed-up is achieved using this technique since the window-based processing of the SICNN is realized in analog-domain while reading the pixel using the modified digital read-out circuit. A prototype including a 58 × 58 pixels and the SICNN processor with a programmable user-defined window size of 3 × 3 or 5 × 5 has been designed. The circuit also includes an amplifier and a successive approximation Analogue-to-digital converter. The circuit has been designed using Alcatel CMOS 0.7 μm technology and occupies a silicon area of 11mm2.

AB - In this paper a real-time mixed analog-digital VLSI implementation of a Shunting Inhibition Cellular Neural Network (SICNN) is presented. Unlike the usual VLSI implementation of vision chips, this circuit is based on a mixed analog-digital technology where the processing is realized using current mode analog approach while the cellular neural network topology (size of the window and connectivity) is realized using a modified digital read-out circuit. A significant processing speed-up is achieved using this technique since the window-based processing of the SICNN is realized in analog-domain while reading the pixel using the modified digital read-out circuit. A prototype including a 58 × 58 pixels and the SICNN processor with a programmable user-defined window size of 3 × 3 or 5 × 5 has been designed. The circuit also includes an amplifier and a successive approximation Analogue-to-digital converter. The circuit has been designed using Alcatel CMOS 0.7 μm technology and occupies a silicon area of 11mm2.

UR - http://www.scopus.com/inward/record.url?scp=0034507522&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034507522&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0034507522

SP - 715

EP - 723

JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

SN - 1520-6130

ER -