Microshift: An Efficient Image Compression Algorithm for Hardware

Bo Zhang, Pedro V. Sander, Chi Ying Tsui, Amine Bermak

Research output: Contribution to journalArticle


In this paper, we propose a lossy image compression algorithm called Microshift. We employ an algorithm-hardware co-design methodology, yielding a hardware friendly compression approach with low power consumption. In our method, the image is first micro-shifted, then the sub-quantized values are further compressed. Two methods, FAST and MRF model, are proposed to recover the bitdepth by exploiting the spatial correlation of natural images. Both methods can decompress images progressively. On average, our compression algorithm can compress images to 1.25 bits per pixel with a resulting quality that outperforms stateof- the-art on-chip compression algorithms in both peak signalto- noise ratio (PSNR) and structual similarity (SSIM). Then, we propose a hardware architecture and implement the algorithm on an FPGA. The results on the ASIC design further validate the low hardware complexity and high power efficiency, showing our method is promising, particularly for low-power wireless vision sensor networks

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems for Video Technology
Publication statusAccepted/In press - 1 Jan 2018



  • Complexity theory
  • Compression algorithms
  • FPGA implementation
  • Hardware
  • Image coding
  • Image quality
  • image sensor
  • Microshift
  • MRF model
  • on-chip image compression
  • Quantization (signal)
  • Uncertainty

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

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