Mapping tensor products onto VLSI networks with reduced I/O

A. Elnaggar, Hussein Alnuweiri, M. R. Ito

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

This paper presents a methodology for designing folded VLSI networks for implementing tensor-product forms. Using tensor-products leads to very efficient expressions for a large number of computations in digital signal processing and matrix arithmetic. The resulting networks can trade-off total time delay with I/O bandwidth and chip area. The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length. Our methods result in folded VLSI networks with optimal AT2 trade-off for digital filtering and multidimensional transforms, where A is the total area of the VLSI circuit (or chip) and T is its total time delay.

Original languageEnglish
Pages (from-to)150-155
Number of pages6
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
Publication statusPublished - 1 Dec 1994
Externally publishedYes

Fingerprint

Tensors
Time delay
VLSI circuits
Digital signal processing
Packaging
Wire
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Mapping tensor products onto VLSI networks with reduced I/O. / Elnaggar, A.; Alnuweiri, Hussein; Ito, M. R.

In: Proceedings of the IEEE Great Lakes Symposium on VLSI, 01.12.1994, p. 150-155.

Research output: Contribution to journalConference article

@article{aaa333f5e36b42a9af249f98a06ed459,
title = "Mapping tensor products onto VLSI networks with reduced I/O",
abstract = "This paper presents a methodology for designing folded VLSI networks for implementing tensor-product forms. Using tensor-products leads to very efficient expressions for a large number of computations in digital signal processing and matrix arithmetic. The resulting networks can trade-off total time delay with I/O bandwidth and chip area. The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length. Our methods result in folded VLSI networks with optimal AT2 trade-off for digital filtering and multidimensional transforms, where A is the total area of the VLSI circuit (or chip) and T is its total time delay.",
author = "A. Elnaggar and Hussein Alnuweiri and Ito, {M. R.}",
year = "1994",
month = "12",
day = "1",
language = "English",
pages = "150--155",
journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",
issn = "1066-1395",
publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - Mapping tensor products onto VLSI networks with reduced I/O

AU - Elnaggar, A.

AU - Alnuweiri, Hussein

AU - Ito, M. R.

PY - 1994/12/1

Y1 - 1994/12/1

N2 - This paper presents a methodology for designing folded VLSI networks for implementing tensor-product forms. Using tensor-products leads to very efficient expressions for a large number of computations in digital signal processing and matrix arithmetic. The resulting networks can trade-off total time delay with I/O bandwidth and chip area. The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length. Our methods result in folded VLSI networks with optimal AT2 trade-off for digital filtering and multidimensional transforms, where A is the total area of the VLSI circuit (or chip) and T is its total time delay.

AB - This paper presents a methodology for designing folded VLSI networks for implementing tensor-product forms. Using tensor-products leads to very efficient expressions for a large number of computations in digital signal processing and matrix arithmetic. The resulting networks can trade-off total time delay with I/O bandwidth and chip area. The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length. Our methods result in folded VLSI networks with optimal AT2 trade-off for digital filtering and multidimensional transforms, where A is the total area of the VLSI circuit (or chip) and T is its total time delay.

UR - http://www.scopus.com/inward/record.url?scp=0028758643&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028758643&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0028758643

SP - 150

EP - 155

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

SN - 1066-1395

ER -