Low-power CMOS image sensor based on column-parallel single-slope/SAR quantization scheme

Fang Tang, Denis Guangyin Chen, Bo Wang, Amine Bermak

Research output: Contribution to journalArticle

29 Citations (Scopus)

Abstract

This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 × 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-μ CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply.

Original languageEnglish
Article number6547236
Pages (from-to)2561-2566
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume60
Issue number8
DOIs
Publication statusPublished - 2013
Externally publishedYes

Fingerprint

Digital to analog conversion
Image sensors
Electric power utilization
Capacitors
Pixels
Color
Electric potential

Keywords

  • APS
  • CMOS image sensor
  • Low power
  • SAR
  • Single slope

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Low-power CMOS image sensor based on column-parallel single-slope/SAR quantization scheme. / Tang, Fang; Chen, Denis Guangyin; Wang, Bo; Bermak, Amine.

In: IEEE Transactions on Electron Devices, Vol. 60, No. 8, 6547236, 2013, p. 2561-2566.

Research output: Contribution to journalArticle

@article{b59f2ff88d56415ba5f65dad216859cf,
title = "Low-power CMOS image sensor based on column-parallel single-slope/SAR quantization scheme",
abstract = "This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 × 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-μ CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply.",
keywords = "APS, CMOS image sensor, Low power, SAR, Single slope",
author = "Fang Tang and Chen, {Denis Guangyin} and Bo Wang and Amine Bermak",
year = "2013",
doi = "10.1109/TED.2013.2268207",
language = "English",
volume = "60",
pages = "2561--2566",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Low-power CMOS image sensor based on column-parallel single-slope/SAR quantization scheme

AU - Tang, Fang

AU - Chen, Denis Guangyin

AU - Wang, Bo

AU - Bermak, Amine

PY - 2013

Y1 - 2013

N2 - This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 × 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-μ CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply.

AB - This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 × 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-μ CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply.

KW - APS

KW - CMOS image sensor

KW - Low power

KW - SAR

KW - Single slope

UR - http://www.scopus.com/inward/record.url?scp=84880916265&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84880916265&partnerID=8YFLogxK

U2 - 10.1109/TED.2013.2268207

DO - 10.1109/TED.2013.2268207

M3 - Article

AN - SCOPUS:84880916265

VL - 60

SP - 2561

EP - 2566

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 8

M1 - 6547236

ER -