Low-power CMOS image sensor based on column-parallel single-slope/SAR quantization scheme

Fang Tang, Denis Guangyin Chen, Bo Wang, Amine Bermak

Research output: Contribution to journalArticle

30 Citations (Scopus)


This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 × 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-μ CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply.

Original languageEnglish
Article number6547236
Pages (from-to)2561-2566
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number8
Publication statusPublished - 2013
Externally publishedYes



  • APS
  • CMOS image sensor
  • Low power
  • SAR
  • Single slope

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this