Low-power and high-speed current-mode CMOS imager with 1T biasing scheme

Fang Tang, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A low-power and high-speed current-mode CMOS image sensor is proposed in this paper. Only one column-level transistor is used in the read-out circuit as a current conveyor to bias the in-pixel transistor operating in triode region. As a result, the current-mode read-out circuit is significantly simplified by the proposed structure, while saving the power by more than half. The proposed scheme enables less than 20ns output settling time due to very low impedance at the internal high capacitance bus, leading to fast operating speed. In addition, a relevant CDS technique is also proposed in order to reduce the first order coefficient variation. A test structure is fabricated using a CMOS 0.35μm process.

Original languageEnglish
Title of host publicationIEEE Sensors 2010 Conference, SENSORS 2010
Pages1653-1656
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2010
Event9th IEEE Sensors Conference 2010, SENSORS 2010 - Waikoloa, HI, United States
Duration: 1 Nov 20104 Nov 2010

Publication series

NameProceedings of IEEE Sensors

Other

Other9th IEEE Sensors Conference 2010, SENSORS 2010
CountryUnited States
CityWaikoloa, HI
Period1/11/104/11/10

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tang, F., & Bermak, A. (2010). Low-power and high-speed current-mode CMOS imager with 1T biasing scheme. In IEEE Sensors 2010 Conference, SENSORS 2010 (pp. 1653-1656). [5689949] (Proceedings of IEEE Sensors). https://doi.org/10.1109/ICSENS.2010.5689949