Highly parallel VLSI architectures for linear convolution

A. Elnaggar, Hussein Alnuweiri, M. R. Ito

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom's algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et. al. [4]. The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.

Original languageEnglish
Pages (from-to)1424-1427
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
Publication statusPublished - 1 Jan 1995
Externally publishedYes

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Adders
Factorization
Convolution
Tensors
Topology

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Highly parallel VLSI architectures for linear convolution. / Elnaggar, A.; Alnuweiri, Hussein; Ito, M. R.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 01.01.1995, p. 1424-1427.

Research output: Contribution to journalConference article

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