High-speed cell scheduling for router backplanes

D. N. Serpanos, P. I. Antoniadis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The performance of the Internet and intranets depends heavily on the characteristics of routers. The use of switched backplanes in routers provides an important direction in communication system architecture and promises to increase dramatically their ability to switch IP packets. We describe the main features of router architectures focusing on schedulers for switched backplanes. We introduce a classification for available algorithms identifying their basic features. We demonstrate that new schedulers can be developed by enforcing fairness and by incorporating features that have been used separately in the past as the classification shows. This leads to switches that provide higher performance than conventional ones, as we demonstrate with the description of a class of such algorithms.

Original languageEnglish
Title of host publicationIEEE International Conference on High Performance Switching and Routing, HPSR
PublisherIEEE Computer Society
Pages65-71
Number of pages7
ISBN (Print)0780358848, 9780780358843
DOIs
Publication statusPublished - 1 Jan 2000
Externally publishedYes
Event2000 IEEE Conference on High Performance Switching and Routing, ATM 2000 - Joint IEEE ATM Workshop 2000 and 3rd International Conference on ATM, ICATM 2000 - Heidelberg, Germany
Duration: 26 Jun 200029 Jun 2000

Other

Other2000 IEEE Conference on High Performance Switching and Routing, ATM 2000 - Joint IEEE ATM Workshop 2000 and 3rd International Conference on ATM, ICATM 2000
CountryGermany
CityHeidelberg
Period26/6/0029/6/00

Fingerprint

Routers
Scheduling
Switches
Intranets
Communication systems
Internet

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Serpanos, D. N., & Antoniadis, P. I. (2000). High-speed cell scheduling for router backplanes. In IEEE International Conference on High Performance Switching and Routing, HPSR (pp. 65-71). [856648] IEEE Computer Society. https://doi.org/10.1109/HPSR.2000.856648

High-speed cell scheduling for router backplanes. / Serpanos, D. N.; Antoniadis, P. I.

IEEE International Conference on High Performance Switching and Routing, HPSR. IEEE Computer Society, 2000. p. 65-71 856648.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Serpanos, DN & Antoniadis, PI 2000, High-speed cell scheduling for router backplanes. in IEEE International Conference on High Performance Switching and Routing, HPSR., 856648, IEEE Computer Society, pp. 65-71, 2000 IEEE Conference on High Performance Switching and Routing, ATM 2000 - Joint IEEE ATM Workshop 2000 and 3rd International Conference on ATM, ICATM 2000, Heidelberg, Germany, 26/6/00. https://doi.org/10.1109/HPSR.2000.856648
Serpanos DN, Antoniadis PI. High-speed cell scheduling for router backplanes. In IEEE International Conference on High Performance Switching and Routing, HPSR. IEEE Computer Society. 2000. p. 65-71. 856648 https://doi.org/10.1109/HPSR.2000.856648
Serpanos, D. N. ; Antoniadis, P. I. / High-speed cell scheduling for router backplanes. IEEE International Conference on High Performance Switching and Routing, HPSR. IEEE Computer Society, 2000. pp. 65-71
@inproceedings{a12028b2d0904258abed4a7327a3b342,
title = "High-speed cell scheduling for router backplanes",
abstract = "The performance of the Internet and intranets depends heavily on the characteristics of routers. The use of switched backplanes in routers provides an important direction in communication system architecture and promises to increase dramatically their ability to switch IP packets. We describe the main features of router architectures focusing on schedulers for switched backplanes. We introduce a classification for available algorithms identifying their basic features. We demonstrate that new schedulers can be developed by enforcing fairness and by incorporating features that have been used separately in the past as the classification shows. This leads to switches that provide higher performance than conventional ones, as we demonstrate with the description of a class of such algorithms.",
author = "Serpanos, {D. N.} and Antoniadis, {P. I.}",
year = "2000",
month = "1",
day = "1",
doi = "10.1109/HPSR.2000.856648",
language = "English",
isbn = "0780358848",
pages = "65--71",
booktitle = "IEEE International Conference on High Performance Switching and Routing, HPSR",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - High-speed cell scheduling for router backplanes

AU - Serpanos, D. N.

AU - Antoniadis, P. I.

PY - 2000/1/1

Y1 - 2000/1/1

N2 - The performance of the Internet and intranets depends heavily on the characteristics of routers. The use of switched backplanes in routers provides an important direction in communication system architecture and promises to increase dramatically their ability to switch IP packets. We describe the main features of router architectures focusing on schedulers for switched backplanes. We introduce a classification for available algorithms identifying their basic features. We demonstrate that new schedulers can be developed by enforcing fairness and by incorporating features that have been used separately in the past as the classification shows. This leads to switches that provide higher performance than conventional ones, as we demonstrate with the description of a class of such algorithms.

AB - The performance of the Internet and intranets depends heavily on the characteristics of routers. The use of switched backplanes in routers provides an important direction in communication system architecture and promises to increase dramatically their ability to switch IP packets. We describe the main features of router architectures focusing on schedulers for switched backplanes. We introduce a classification for available algorithms identifying their basic features. We demonstrate that new schedulers can be developed by enforcing fairness and by incorporating features that have been used separately in the past as the classification shows. This leads to switches that provide higher performance than conventional ones, as we demonstrate with the description of a class of such algorithms.

UR - http://www.scopus.com/inward/record.url?scp=84905367131&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84905367131&partnerID=8YFLogxK

U2 - 10.1109/HPSR.2000.856648

DO - 10.1109/HPSR.2000.856648

M3 - Conference contribution

AN - SCOPUS:84905367131

SN - 0780358848

SN - 9780780358843

SP - 65

EP - 71

BT - IEEE International Conference on High Performance Switching and Routing, HPSR

PB - IEEE Computer Society

ER -