High-performance hardware implementation for RC4 stream cipher

Sourav Sen Gupta, Anupam Chattopadhyay, Koushik Sinha, Subhamoy Maitra, Bhabani P. Sinha

Research output: Contribution to journalArticle

46 Citations (Scopus)

Abstract

RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces 2 RC4 keystream bytes per clock cycle. We have optimized and implemented our proposed design using VHDL description, synthesized with 130, 90, and 65 nm fabrication technologies at clock frequencies 625 MHz, 1.37 GHz, and 1.92 GHz, respectively, to obtain a final RC4 keystream throughput of 10, 21.92, and 30.72 Gbps in the respective technologies.

Original languageEnglish
Article number6133271
Pages (from-to)730-743
Number of pages14
JournalIEEE Transactions on Computers
Volume62
Issue number4
DOIs
Publication statusPublished - 18 Mar 2013
Externally publishedYes

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Keywords

  • Cryptography
  • hardware accelerator
  • high throughput
  • loop unrolling
  • pipelining
  • RC4
  • stream cipher

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

Sen Gupta, S., Chattopadhyay, A., Sinha, K., Maitra, S., & Sinha, B. P. (2013). High-performance hardware implementation for RC4 stream cipher. IEEE Transactions on Computers, 62(4), 730-743. [6133271]. https://doi.org/10.1109/TC.2012.19