High-performance hardware implementation for RC4 stream cipher

Sourav Sen Gupta, Anupam Chattopadhyay, Koushik Sinha, Subhamoy Maitra, Bhabani P. Sinha

Research output: Contribution to journalArticle

45 Citations (Scopus)

Abstract

RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces 2 RC4 keystream bytes per clock cycle. We have optimized and implemented our proposed design using VHDL description, synthesized with 130, 90, and 65 nm fabrication technologies at clock frequencies 625 MHz, 1.37 GHz, and 1.92 GHz, respectively, to obtain a final RC4 keystream throughput of 10, 21.92, and 30.72 Gbps in the respective technologies.

Original languageEnglish
Article number6133271
Pages (from-to)730-743
Number of pages14
JournalIEEE Transactions on Computers
Volume62
Issue number4
DOIs
Publication statusPublished - 18 Mar 2013
Externally publishedYes

Fingerprint

Stream Cipher
Hardware Implementation
Clocks
High Performance
Hardware
Cryptology
Computer hardware description languages
Fabrication
Throughput
Pipelines
Cycle
Design
Architecture

Keywords

  • Cryptography
  • hardware accelerator
  • high throughput
  • loop unrolling
  • pipelining
  • RC4
  • stream cipher

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

Sen Gupta, S., Chattopadhyay, A., Sinha, K., Maitra, S., & Sinha, B. P. (2013). High-performance hardware implementation for RC4 stream cipher. IEEE Transactions on Computers, 62(4), 730-743. [6133271]. https://doi.org/10.1109/TC.2012.19

High-performance hardware implementation for RC4 stream cipher. / Sen Gupta, Sourav; Chattopadhyay, Anupam; Sinha, Koushik; Maitra, Subhamoy; Sinha, Bhabani P.

In: IEEE Transactions on Computers, Vol. 62, No. 4, 6133271, 18.03.2013, p. 730-743.

Research output: Contribution to journalArticle

Sen Gupta, S, Chattopadhyay, A, Sinha, K, Maitra, S & Sinha, BP 2013, 'High-performance hardware implementation for RC4 stream cipher', IEEE Transactions on Computers, vol. 62, no. 4, 6133271, pp. 730-743. https://doi.org/10.1109/TC.2012.19
Sen Gupta S, Chattopadhyay A, Sinha K, Maitra S, Sinha BP. High-performance hardware implementation for RC4 stream cipher. IEEE Transactions on Computers. 2013 Mar 18;62(4):730-743. 6133271. https://doi.org/10.1109/TC.2012.19
Sen Gupta, Sourav ; Chattopadhyay, Anupam ; Sinha, Koushik ; Maitra, Subhamoy ; Sinha, Bhabani P. / High-performance hardware implementation for RC4 stream cipher. In: IEEE Transactions on Computers. 2013 ; Vol. 62, No. 4. pp. 730-743.
@article{bf3deb4a12c3488aa680de56b35c404c,
title = "High-performance hardware implementation for RC4 stream cipher",
abstract = "RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces 2 RC4 keystream bytes per clock cycle. We have optimized and implemented our proposed design using VHDL description, synthesized with 130, 90, and 65 nm fabrication technologies at clock frequencies 625 MHz, 1.37 GHz, and 1.92 GHz, respectively, to obtain a final RC4 keystream throughput of 10, 21.92, and 30.72 Gbps in the respective technologies.",
keywords = "Cryptography, hardware accelerator, high throughput, loop unrolling, pipelining, RC4, stream cipher",
author = "{Sen Gupta}, Sourav and Anupam Chattopadhyay and Koushik Sinha and Subhamoy Maitra and Sinha, {Bhabani P.}",
year = "2013",
month = "3",
day = "18",
doi = "10.1109/TC.2012.19",
language = "English",
volume = "62",
pages = "730--743",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "4",

}

TY - JOUR

T1 - High-performance hardware implementation for RC4 stream cipher

AU - Sen Gupta, Sourav

AU - Chattopadhyay, Anupam

AU - Sinha, Koushik

AU - Maitra, Subhamoy

AU - Sinha, Bhabani P.

PY - 2013/3/18

Y1 - 2013/3/18

N2 - RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces 2 RC4 keystream bytes per clock cycle. We have optimized and implemented our proposed design using VHDL description, synthesized with 130, 90, and 65 nm fabrication technologies at clock frequencies 625 MHz, 1.37 GHz, and 1.92 GHz, respectively, to obtain a final RC4 keystream throughput of 10, 21.92, and 30.72 Gbps in the respective technologies.

AB - RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces 2 RC4 keystream bytes per clock cycle. We have optimized and implemented our proposed design using VHDL description, synthesized with 130, 90, and 65 nm fabrication technologies at clock frequencies 625 MHz, 1.37 GHz, and 1.92 GHz, respectively, to obtain a final RC4 keystream throughput of 10, 21.92, and 30.72 Gbps in the respective technologies.

KW - Cryptography

KW - hardware accelerator

KW - high throughput

KW - loop unrolling

KW - pipelining

KW - RC4

KW - stream cipher

UR - http://www.scopus.com/inward/record.url?scp=84872187481&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84872187481&partnerID=8YFLogxK

U2 - 10.1109/TC.2012.19

DO - 10.1109/TC.2012.19

M3 - Article

AN - SCOPUS:84872187481

VL - 62

SP - 730

EP - 743

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 4

M1 - 6133271

ER -