High fill-factor native logarithmic pixel

Simulation, design and layout optimization

Amine Bermak, Abdesslam Bouzerdoum, Kamran Eshraghian

Research output: Contribution to journalArticle

14 Citations (Scopus)

Abstract

In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
Publication statusPublished - 2000
Externally publishedYes

Fingerprint

Pixels
Bandwidth
Transistors
Planning

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

High fill-factor native logarithmic pixel : Simulation, design and layout optimization. / Bermak, Amine; Bouzerdoum, Abdesslam; Eshraghian, Kamran.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 5, 2000.

Research output: Contribution to journalArticle

@article{e3567c22e224442ebe96f0937f81b994,
title = "High fill-factor native logarithmic pixel: Simulation, design and layout optimization",
abstract = "In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46{\%} fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.",
author = "Amine Bermak and Abdesslam Bouzerdoum and Kamran Eshraghian",
year = "2000",
language = "English",
volume = "5",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - High fill-factor native logarithmic pixel

T2 - Simulation, design and layout optimization

AU - Bermak, Amine

AU - Bouzerdoum, Abdesslam

AU - Eshraghian, Kamran

PY - 2000

Y1 - 2000

N2 - In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.

AB - In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=0033702502&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033702502&partnerID=8YFLogxK

M3 - Article

VL - 5

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -