High-density 16/8/4-bit configurable multiplier

A. Bermak, D. Martinez, J. L. Noullet

Research output: Contribution to journalArticle

15 Citations (Scopus)

Abstract

A configurable serial-parallel multiplier based on Braun's and Baugh-Wooley's algorithms is presented. The multiplier can be configured to perform either signed or unsigned multiplications and to achieve variable precision. In this device one factor A(m) is fed serially with an arbitrary wordlength m while the other B(n) is stored in parallel with a configurable number of bits n = 4, 8 or 16 bits. Switch elements are used to change the hardware connection between adjacent 4-bit multiplier basic blocks. This reconfiguration concept provides a higher precision multiplier by grouping adjacent cells or a higher throughput at low levels of precisions. A prototype of this multiplier has been fabricated using a full custom 1.0μm CMOS technology. The active area contains 3450 transistors and occupies 0.47mm2 corresponding to a very high gate density of 1532 gates/mm2.

Original languageEnglish
Pages (from-to)272-276
Number of pages5
JournalIEE Proceedings: Circuits, Devices and Systems
Volume144
Issue number5
DOIs
Publication statusPublished - 1 Jan 1997

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Keywords

  • Configurable multiplier
  • Multiprecision computation
  • Serial-parallel multiplier
  • Vlsi multiplier

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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