FPGA-based transformable coprocessor for MPEG video processing

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1 Citation (Scopus)

Abstract

This paper demonstrates how an FPGA-based transformable coprocessor can be used to implement a real-time MPEG-1 video decoder with enhanced features. The transformable coprocessor consists of an FPGA, local static RAM, and a host bus interface built into the FPGA. The gate-limited FPGA core is reconfigured frequently to implement various parts of the video decoding process in real-time. Our results show that, through reconfiguration, FPGA-based processors can handle complex tasks (such as high-quality video decoding) adequately. We also identify the major bottlenecks that impede achieving higher speedups with the FPGAs. For MPEG-1 video processing, the major slowdown is caused by the excessive data transfers and bottlenecks due to bus interfaces and lack of sufficient storage in FPGA.

Original languageEnglish
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
EditorsJohn Schewel, Peter M. Athanas, V.Michael Jr. Bove, John Watson
Pages308-320
Number of pages13
Volume2914
Publication statusPublished - 1 Dec 1996
Externally publishedYes
EventHigh-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic - Boston, MA, USA
Duration: 20 Nov 199621 Nov 1996

Other

OtherHigh-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic
CityBoston, MA, USA
Period20/11/9621/11/96

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chow, H., & Alnuweiri, H. (1996). FPGA-based transformable coprocessor for MPEG video processing. In J. Schewel, P. M. Athanas, V. M. J. Bove, & J. Watson (Eds.), Proceedings of SPIE - The International Society for Optical Engineering (Vol. 2914, pp. 308-320)