Focal plane image segmentation using locally interconnected spiking pixel architecture

Amine Bermak, Matthias Hofinger

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper we describe a focal-plane image segmentation architecture using an array of spiking pixels. We first describe the spiking pixel architecture which can be used in a locally interconnected network in order to perform image capture as well as image segmentation. Inspired from Biological visual systems and the integrate and fire oscillator, three different schemes are studied and their ability to perform image segmentation is compared. Simulation results demonstrate that heavy computational processing such as image segmentation can be realized with spiking pixel architecture organized in locally interconnected networks allowing them to be very suitable for VLSI implementation. Each pixel within the focal plane processing image sensor occupies an area of only 45 × 45μm2 using CMOS 0.25μm technology.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
Publication statusPublished - 2003
Externally publishedYes

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Image segmentation
Pixels
Processing
Image sensors
Fires

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

@article{e517500a1d404e26a17fe400f2acc47b,
title = "Focal plane image segmentation using locally interconnected spiking pixel architecture",
abstract = "In this paper we describe a focal-plane image segmentation architecture using an array of spiking pixels. We first describe the spiking pixel architecture which can be used in a locally interconnected network in order to perform image capture as well as image segmentation. Inspired from Biological visual systems and the integrate and fire oscillator, three different schemes are studied and their ability to perform image segmentation is compared. Simulation results demonstrate that heavy computational processing such as image segmentation can be realized with spiking pixel architecture organized in locally interconnected networks allowing them to be very suitable for VLSI implementation. Each pixel within the focal plane processing image sensor occupies an area of only 45 × 45μm2 using CMOS 0.25μm technology.",
author = "Amine Bermak and Matthias Hofinger",
year = "2003",
language = "English",
volume = "5",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Focal plane image segmentation using locally interconnected spiking pixel architecture

AU - Bermak, Amine

AU - Hofinger, Matthias

PY - 2003

Y1 - 2003

N2 - In this paper we describe a focal-plane image segmentation architecture using an array of spiking pixels. We first describe the spiking pixel architecture which can be used in a locally interconnected network in order to perform image capture as well as image segmentation. Inspired from Biological visual systems and the integrate and fire oscillator, three different schemes are studied and their ability to perform image segmentation is compared. Simulation results demonstrate that heavy computational processing such as image segmentation can be realized with spiking pixel architecture organized in locally interconnected networks allowing them to be very suitable for VLSI implementation. Each pixel within the focal plane processing image sensor occupies an area of only 45 × 45μm2 using CMOS 0.25μm technology.

AB - In this paper we describe a focal-plane image segmentation architecture using an array of spiking pixels. We first describe the spiking pixel architecture which can be used in a locally interconnected network in order to perform image capture as well as image segmentation. Inspired from Biological visual systems and the integrate and fire oscillator, three different schemes are studied and their ability to perform image segmentation is compared. Simulation results demonstrate that heavy computational processing such as image segmentation can be realized with spiking pixel architecture organized in locally interconnected networks allowing them to be very suitable for VLSI implementation. Each pixel within the focal plane processing image sensor occupies an area of only 45 × 45μm2 using CMOS 0.25μm technology.

UR - http://www.scopus.com/inward/record.url?scp=0038419790&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038419790&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0038419790

VL - 5

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -