In this paper we describe a focal-plane image segmentation architecture using an array of spiking pixels. We first describe the spiking pixel architecture which can be used in a locally interconnected network in order to perform image capture as well as image segmentation. Inspired from Biological visual systems and the integrate and fire oscillator, three different schemes are studied and their ability to perform image segmentation is compared. Simulation results demonstrate that heavy computational processing such as image segmentation can be realized with spiking pixel architecture organized in locally interconnected networks allowing them to be very suitable for VLSI implementation. Each pixel within the focal plane processing image sensor occupies an area of only 45 × 45μm2 using CMOS 0.25μm technology.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 14 Jul 2003|
|Event||Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand|
Duration: 25 May 2003 → 28 May 2003
ASJC Scopus subject areas
- Electrical and Electronic Engineering