Fast VLSI chip for computing the two-dimensional discrete cosine transform

William S. Wong, Anthony Berno, Hussein M. Alnuweiri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A VLSI chip which performs an 8-point Discrete Cosine Transform using Distributed Arithmetic and Li's algorithm has been successfully designed and tested. Its total throughput is as high as 250 Mbits per second, which is of the order required for real-time applications such as the compression of video. Both the size and performance of the chip can be substantially improved through changes in its technology and design. Work on a 2-D DCT processor based on this unit is in progress.

Original languageEnglish
Title of host publicationProc IEEE 1993 Pac Rim Conf Commun Comput Signal Process
PublisherPubl by IEEE
Pages662-665
Number of pages4
ISBN (Print)0780312198
Publication statusPublished - 1 Jan 1993
EventProceedings of the IEEE 1993 Pacific Rim Conference on Communications, Computers and Signal Processing - Victoria, BC, Can
Duration: 19 May 199321 May 1993

Publication series

NameProc IEEE 1993 Pac Rim Conf Commun Comput Signal Process

Other

OtherProceedings of the IEEE 1993 Pacific Rim Conference on Communications, Computers and Signal Processing
CityVictoria, BC, Can
Period19/5/9321/5/93

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wong, W. S., Berno, A., & Alnuweiri, H. M. (1993). Fast VLSI chip for computing the two-dimensional discrete cosine transform. In Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process (pp. 662-665). (Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process). Publ by IEEE.