Fast timing recovery for linearly and nonlinearly modulated systems

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Digital phase lock loops (PLLs) are often used in timing acquisition systems. It is known that some non-data-aided timing error detectors occasionally cause hangup problems in digital PLLs. In this paper, we introduce a novel two step antihangup timing recovery scheme. Through intensive simulations, we show that this enhanced scheme greatly reduces the probability of hangup, and speeds up the timing recovery process for both linearly and nonlinearly modulated systems.

Original languageEnglish
Pages (from-to)2017-2023
Number of pages7
JournalIEEE Transactions on Vehicular Technology
Volume54
Issue number6
DOIs
Publication statusPublished - 1 Nov 2005

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Keywords

  • Digital phase lockloop (PLL)
  • Fast acquisition
  • Feedback
  • Hangup
  • Linear modulations
  • Nonlinear modulations
  • Timing error detector
  • Timing recovery

ASJC Scopus subject areas

  • Automotive Engineering
  • Aerospace Engineering
  • Electrical and Electronic Engineering
  • Applied Mathematics

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