### Abstract

This paper presents a VLSI array for labeling the connected components of a graph on N nodes in O(r) steps using a reconfigurable bus of width m bits, such that (_{r}^{m})≥N and 1≤r≤m. The network architecture consists of an array of simple logic nodes which are connected by a reconfigurable bus.To solve a problem on N nodes, the array uses N processors and N(N-1)/2 switches. The proposed connectivity and transitive closure algorithms are based on a processor indexing scheme which employs constant-weight codes. It is shown that when r is a constant, then the algorithm takes O(1) time using a bus of width O(N^{1/r}), and when r = [log N/loglog N], the algorithm takes O(log N/loglog N) time using a bus or width O(log N) bits.

Original language | English |
---|---|

Pages (from-to) | 105-115 |

Number of pages | 11 |

Journal | Parallel Processing Letters |

Volume | 4 |

Issue number | 1-2 |

Publication status | Published - 1 Jun 1994 |

Externally published | Yes |

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### ASJC Scopus subject areas

- Computer Science(all)
- Engineering(all)

### Cite this

*Parallel Processing Letters*,

*4*(1-2), 105-115.

**Fast reconfigurable network for graph connectivity and transitive closure.** / Alnuweiri, Hussein.

Research output: Contribution to journal › Article

*Parallel Processing Letters*, vol. 4, no. 1-2, pp. 105-115.

}

TY - JOUR

T1 - Fast reconfigurable network for graph connectivity and transitive closure

AU - Alnuweiri, Hussein

PY - 1994/6/1

Y1 - 1994/6/1

N2 - This paper presents a VLSI array for labeling the connected components of a graph on N nodes in O(r) steps using a reconfigurable bus of width m bits, such that (rm)≥N and 1≤r≤m. The network architecture consists of an array of simple logic nodes which are connected by a reconfigurable bus.To solve a problem on N nodes, the array uses N processors and N(N-1)/2 switches. The proposed connectivity and transitive closure algorithms are based on a processor indexing scheme which employs constant-weight codes. It is shown that when r is a constant, then the algorithm takes O(1) time using a bus of width O(N1/r), and when r = [log N/loglog N], the algorithm takes O(log N/loglog N) time using a bus or width O(log N) bits.

AB - This paper presents a VLSI array for labeling the connected components of a graph on N nodes in O(r) steps using a reconfigurable bus of width m bits, such that (rm)≥N and 1≤r≤m. The network architecture consists of an array of simple logic nodes which are connected by a reconfigurable bus.To solve a problem on N nodes, the array uses N processors and N(N-1)/2 switches. The proposed connectivity and transitive closure algorithms are based on a processor indexing scheme which employs constant-weight codes. It is shown that when r is a constant, then the algorithm takes O(1) time using a bus of width O(N1/r), and when r = [log N/loglog N], the algorithm takes O(log N/loglog N) time using a bus or width O(log N) bits.

UR - http://www.scopus.com/inward/record.url?scp=0028450243&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028450243&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0028450243

VL - 4

SP - 105

EP - 115

JO - Parallel Processing Letters

JF - Parallel Processing Letters

SN - 0129-6264

IS - 1-2

ER -