Fast reconfigurable network for graph connectivity and transitive closure

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This paper presents a VLSI array for labeling the connected components of a graph on N nodes in O(r) steps using a reconfigurable bus of width m bits, such that (rm)≥N and 1≤r≤m. The network architecture consists of an array of simple logic nodes which are connected by a reconfigurable bus.To solve a problem on N nodes, the array uses N processors and N(N-1)/2 switches. The proposed connectivity and transitive closure algorithms are based on a processor indexing scheme which employs constant-weight codes. It is shown that when r is a constant, then the algorithm takes O(1) time using a bus of width O(N1/r), and when r = [log N/loglog N], the algorithm takes O(log N/loglog N) time using a bus or width O(log N) bits.

Original languageEnglish
Pages (from-to)105-115
Number of pages11
JournalParallel Processing Letters
Volume4
Issue number1-2
Publication statusPublished - 1 Jun 1994
Externally publishedYes

Fingerprint

Container closures
Graph Connectivity
Transitive Closure
Vertex of a graph
Constant Weight Codes
Network Architecture
Connected Components
Indexing
Labeling
Switch
Connectivity
Network architecture
Logic
Switches
Graph in graph theory

ASJC Scopus subject areas

  • Computer Science(all)
  • Engineering(all)

Cite this

Fast reconfigurable network for graph connectivity and transitive closure. / Alnuweiri, Hussein.

In: Parallel Processing Letters, Vol. 4, No. 1-2, 01.06.1994, p. 105-115.

Research output: Contribution to journalArticle

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