### Abstract

This paper presents constant-time algorithms for labeling the connected components of images on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an NN image or an N-vertex graph in O(1) time using Theta (N^{2}) processors, which is optimal. Furthermore, the proposed techniques lead to O(log N/log log N)-time labeling algorithms on a network of N^{2} processors with a reconfigurable bus of width O(log N) bits.

Original language | English |
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Title of host publication | Proceedings of 7th International Parallel Processing Symposium, IPPS 1993 |

Publisher | Institute of Electrical and Electronics Engineers Inc. |

Pages | 569-575 |

Number of pages | 7 |

ISBN (Electronic) | 0818634421, 9780818634420 |

DOIs | |

Publication status | Published - 1 Jan 1993 |

Event | 7th International Parallel Processing Symposium, IPPS 1993 - Newport, United States Duration: 13 Apr 1993 → 16 Apr 1993 |

### Publication series

Name | Proceedings of 7th International Parallel Processing Symposium, IPPS 1993 |
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### Conference

Conference | 7th International Parallel Processing Symposium, IPPS 1993 |
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Country | United States |

City | Newport |

Period | 13/4/93 → 16/4/93 |

### Fingerprint

### ASJC Scopus subject areas

- Computer Science Applications
- Hardware and Architecture
- Software
- Computational Theory and Mathematics
- Computer Networks and Communications

### Cite this

*Proceedings of 7th International Parallel Processing Symposium, IPPS 1993*(pp. 569-575). [262816] (Proceedings of 7th International Parallel Processing Symposium, IPPS 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPPS.1993.262816