Exploring data prefetching mechanisms for last level cache in chip multi-processors

Mingliang Liu, Lin Qiao, Fucen Zeng, Zhizhong Tang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Last level cache in chip multi-processors is shared by many cores; prefetchers should be fully simulated and evaluated before integrated in product. However, evaluation methodologies of proposed prefetchers vary from each other without unified simulation framework provided. This paper implements a prefetch simulation framework and evaluates seven important prefetchers, providing comprehensive evaluation methodology to newly proposed prefetchers. Moreover, we analyze the influence of storage cost and memory bandwidth quantitatively.

Original languageEnglish
Title of host publicationAdvanced Technology in Teaching - Selected Papers from the 2012 International Conference on Teaching and Computational Science, ICTCS 2012
Pages577-584
Number of pages8
DOIs
Publication statusPublished - 5 Sep 2012
Event2012 International Conference on Teaching and Computational Science, ICTCS 2012 - , Macao
Duration: 1 Apr 20122 Apr 2012

Publication series

NameAdvances in Intelligent and Soft Computing
Volume163 AISC
ISSN (Print)1867-5662

Conference

Conference2012 International Conference on Teaching and Computational Science, ICTCS 2012
CountryMacao
Period1/4/122/4/12

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Keywords

  • cache memories
  • memory control and access
  • performance evaluation
  • simulation

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Liu, M., Qiao, L., Zeng, F., & Tang, Z. (2012). Exploring data prefetching mechanisms for last level cache in chip multi-processors. In Advanced Technology in Teaching - Selected Papers from the 2012 International Conference on Teaching and Computational Science, ICTCS 2012 (pp. 577-584). (Advances in Intelligent and Soft Computing; Vol. 163 AISC). https://doi.org/10.1007/978-3-642-29458-7_83