Evaluation of switch schedulers for embedded systems

D. N. Serpanos, X. Moundrouidou, M. Gambrili

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We evaluate hardware and software implementations of a centralized and a distributed scheduler for embedded packet switches. The evaluation is performed for embedded system implementation, on a system that includes an FPGA and an embedded, on-chip processor. The results demonstrate that, in contrast to expectations, centralized schedulers provide better performance than distributed ones in hardware implementations. In software implementations for embedded processors, surprisingly, distributed schedulers achieve better performance, due to better management of the processor's limited resources and simpler code.

Original languageEnglish
Title of host publicationProceedings - 8th IEEE International Symposium on Computers and Communication, ISCC 2003
Pages541-546
Number of pages6
DOIs
Publication statusPublished - 1 Dec 2003
Event8th IEEE International Symposium on Computers and Communication, ISCC 2003 - Kemer-Antalya, Turkey
Duration: 30 Jun 20033 Jul 2003

Publication series

NameProceedings - IEEE Symposium on Computers and Communications
ISSN (Print)1530-1346

Other

Other8th IEEE International Symposium on Computers and Communication, ISCC 2003
CountryTurkey
CityKemer-Antalya
Period30/6/033/7/03

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ASJC Scopus subject areas

  • Software
  • Signal Processing
  • Mathematics(all)
  • Computer Science Applications
  • Computer Networks and Communications

Cite this

Serpanos, D. N., Moundrouidou, X., & Gambrili, M. (2003). Evaluation of switch schedulers for embedded systems. In Proceedings - 8th IEEE International Symposium on Computers and Communication, ISCC 2003 (pp. 541-546). [1214175] (Proceedings - IEEE Symposium on Computers and Communications). https://doi.org/10.1109/ISCC.2003.1214175