Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures

Eva Papadogiannaki, Lazaros Koromilas, Giorgos Vasiliadis, Sotiris Ioannidis

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Heterogeneous and asymmetric computing systems are composed by a set of different processing units, each with its own unique performance and energy characteristics. Still, the majority of current network packet processing frameworks targets only a single device (the CPU or some accelerator), leaving the rest processing resources unused and idle. In this paper, we propose an adaptive scheduling approach that supports the heterogeneous and asymmetric hardware, tailored for network packet processing applications. Our scheduler is able to respond quickly to dynamic performance fluctuations that occur at real time, such as traffic bursts, application overloads, and system changes. The experimental results show that our system is able to match the peak throughput of a diverse set of packet processing applications, while consuming up to 3.$x less energy.

Original languageEnglish
JournalIEEE/ACM Transactions on Networking
DOIs
Publication statusAccepted/In press - 27 Jan 2017

Fingerprint

Hardware
Processing
Packet networks
Particle accelerators
Program processors
Scheduling
Throughput

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures. / Papadogiannaki, Eva; Koromilas, Lazaros; Vasiliadis, Giorgos; Ioannidis, Sotiris.

In: IEEE/ACM Transactions on Networking, 27.01.2017.

Research output: Contribution to journalArticle

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