Efficient software packet processing on heterogeneous and asymmetric hardware architectures

Lazaros Koromilas, Giorgos Vasiliadis, Ioannis Manousakis, Sotiris Ioannidis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

Heterogeneous and asymmetric computing systems are composed by a set of different processing units, each with its own unique performance and energy characteristics. Still, the majority of current network packet processing frameworks targets only a single device (the CPU or some accelerator), leaving other processing resources idle. In this paper, we propose an adaptive scheduling approach that supports heterogeneous and asymmetric hardware, tailored for network packet processing applications. Our scheduler is able to respond quickly to dynamic performance fluctuations that occur at real-time, such as traffic bursts, application overloads and system changes. The experimental results show that our system is able to match the peak throughput of a diverse set of packet processing workloads, while consuming up to 3.5x less energy.

Original languageEnglish
Title of host publicationANCS 2014 - 10th 2014 ACM/IEEE Symposium on Architectures for Networking and Communications Systems
PublisherAssociation for Computing Machinery, Inc
Pages207-218
Number of pages12
ISBN (Electronic)9781450328395
DOIs
Publication statusPublished - 20 Oct 2014
Externally publishedYes
Event10th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2014 - Marina del Rey, United States
Duration: 20 Oct 201421 Oct 2014

Other

Other10th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2014
CountryUnited States
CityMarina del Rey
Period20/10/1421/10/14

Fingerprint

Hardware
Processing
Packet networks
Particle accelerators
Program processors
Scheduling
Throughput

Keywords

  • Heterogeneous processing
  • OpenCL
  • Packet processing
  • Packet scheduling

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Koromilas, L., Vasiliadis, G., Manousakis, I., & Ioannidis, S. (2014). Efficient software packet processing on heterogeneous and asymmetric hardware architectures. In ANCS 2014 - 10th 2014 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (pp. 207-218). Association for Computing Machinery, Inc. https://doi.org/10.1145/2658260.2658265

Efficient software packet processing on heterogeneous and asymmetric hardware architectures. / Koromilas, Lazaros; Vasiliadis, Giorgos; Manousakis, Ioannis; Ioannidis, Sotiris.

ANCS 2014 - 10th 2014 ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Association for Computing Machinery, Inc, 2014. p. 207-218.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Koromilas, L, Vasiliadis, G, Manousakis, I & Ioannidis, S 2014, Efficient software packet processing on heterogeneous and asymmetric hardware architectures. in ANCS 2014 - 10th 2014 ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Association for Computing Machinery, Inc, pp. 207-218, 10th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2014, Marina del Rey, United States, 20/10/14. https://doi.org/10.1145/2658260.2658265
Koromilas L, Vasiliadis G, Manousakis I, Ioannidis S. Efficient software packet processing on heterogeneous and asymmetric hardware architectures. In ANCS 2014 - 10th 2014 ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Association for Computing Machinery, Inc. 2014. p. 207-218 https://doi.org/10.1145/2658260.2658265
Koromilas, Lazaros ; Vasiliadis, Giorgos ; Manousakis, Ioannis ; Ioannidis, Sotiris. / Efficient software packet processing on heterogeneous and asymmetric hardware architectures. ANCS 2014 - 10th 2014 ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Association for Computing Machinery, Inc, 2014. pp. 207-218
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