Efficient Network Folding Techniques for Routing Permutations in VLSI

Hussein Alnuweiri, Sadiq M. Sait

Research output: Contribution to journalArticle

Abstract

Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M < N. A major motivation for network folding is the severely limited number of I/O pins in microelectronic packages, such as VLSI chips or multichip module (MCM) packages. Cost overhead and performance degradation due to off-chip communication as well as long on-chip wires may render implementing otherwise good designs infeasible or inefficient. In this paper, an efficient and systematic methodology is proposed for designing folded permutation networks that can route the class of bit-permute-complement (BPC) permutations. In particular, it is shown that any folded BPC permutation network can be constructed using only two stages of uniform-size transpose networks. This results in highly modular structures for BPC networks. The methodology trades off speed (time), with I/O and chip-area.

Original languageEnglish
Pages (from-to)254-263
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume3
Issue number2
DOIs
Publication statusPublished - 1 Jan 1995
Externally publishedYes

Keywords

  • area-time tradeoffs
  • BPC permutations
  • I/O reduction
  • I/O-time tradeoffs
  • network folding
  • permutation routing
  • VLSI interconnection

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Efficient Network Folding Techniques for Routing Permutations in VLSI'. Together they form a unique fingerprint.

  • Cite this