Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

Mohamed S. Khairy, Mohamed M. Abdallah, S. E.D. Habib

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.

Original languageEnglish
Title of host publicationProceediangs - 2008 3rd International Design and Test Workshop, IDT 2008
Pages177-181
Number of pages5
DOIs
Publication statusPublished - 1 Dec 2008
Event2008 3rd International Design and Test Workshop, IDT 2008 - Monastir, Tunisia
Duration: 20 Dec 200822 Dec 2008

Publication series

NameProceedings - 2008 3rd International Design and Test Workshop, IDT 2008

Other

Other2008 3rd International Design and Test Workshop, IDT 2008
CountryTunisia
CityMonastir
Period20/12/0822/12/08

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Keywords

  • FPGA prototyping
  • MIMO systems
  • Sphere decoder
  • Wireless communications

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Khairy, M. S., Abdallah, M. M., & Habib, S. E. D. (2008). Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. In Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008 (pp. 177-181). [4802492] (Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008). https://doi.org/10.1109/IDT.2008.4802492