Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

Mohamed S. Khairy, Mohamed Abdallah, S. E.D. Habib

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.

Original languageEnglish
Title of host publicationProceediangs - 2008 3rd International Design and Test Workshop, IDT 2008
Pages177-181
Number of pages5
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 3rd International Design and Test Workshop, IDT 2008 - Monastir, Tunisia
Duration: 20 Dec 200822 Dec 2008

Other

Other2008 3rd International Design and Test Workshop, IDT 2008
CountryTunisia
CityMonastir
Period20/12/0822/12/08

Fingerprint

MIMO systems
Field programmable gate arrays (FPGA)
Throughput
Hardware
Quadrature amplitude modulation
Modulation

Keywords

  • FPGA prototyping
  • MIMO systems
  • Sphere decoder
  • Wireless communications

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Khairy, M. S., Abdallah, M., & Habib, S. E. D. (2008). Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. In Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008 (pp. 177-181). [4802492] https://doi.org/10.1109/IDT.2008.4802492

Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. / Khairy, Mohamed S.; Abdallah, Mohamed; Habib, S. E.D.

Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008. 2008. p. 177-181 4802492.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Khairy, MS, Abdallah, M & Habib, SED 2008, Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. in Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008., 4802492, pp. 177-181, 2008 3rd International Design and Test Workshop, IDT 2008, Monastir, Tunisia, 20/12/08. https://doi.org/10.1109/IDT.2008.4802492
Khairy MS, Abdallah M, Habib SED. Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. In Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008. 2008. p. 177-181. 4802492 https://doi.org/10.1109/IDT.2008.4802492
Khairy, Mohamed S. ; Abdallah, Mohamed ; Habib, S. E.D. / Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008. 2008. pp. 177-181
@inproceedings{fdc609562a6e4da0980557a54e321e69,
title = "Efficient FPGA prototyping of fixed sphere decoder for MIMO systems",
abstract = "In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.",
keywords = "FPGA prototyping, MIMO systems, Sphere decoder, Wireless communications",
author = "Khairy, {Mohamed S.} and Mohamed Abdallah and Habib, {S. E.D.}",
year = "2008",
doi = "10.1109/IDT.2008.4802492",
language = "English",
isbn = "9781424434770",
pages = "177--181",
booktitle = "Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008",

}

TY - GEN

T1 - Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

AU - Khairy, Mohamed S.

AU - Abdallah, Mohamed

AU - Habib, S. E.D.

PY - 2008

Y1 - 2008

N2 - In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.

AB - In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.

KW - FPGA prototyping

KW - MIMO systems

KW - Sphere decoder

KW - Wireless communications

UR - http://www.scopus.com/inward/record.url?scp=64849089261&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=64849089261&partnerID=8YFLogxK

U2 - 10.1109/IDT.2008.4802492

DO - 10.1109/IDT.2008.4802492

M3 - Conference contribution

AN - SCOPUS:64849089261

SN - 9781424434770

SP - 177

EP - 181

BT - Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008

ER -