Efficient design of scalable shared-memory packet switches

M. Alimuddin, H. M. Alnuweiri, R. W. Donaldson

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

This paper presents a general model for optimizing buffer-bandwidth trade-offs in output-buffered packet switches. It also provides a framework for designing scalable shared-memory ATM switches. The general model is based on small-depth (truncated) switch fabrics which employ a self-routing mechanism, and shared-memory modules to optimize buffer utilization. Bandwidth optimization is achieved using a generalized model for unbuffered dilated banyan networks, while buffer allocation is optimized using output grouping shared-memory modules at the output. This model has two major advantages over the 'growable switch'. First it simplifies the interconnect fabric by using self-routing truncated fabric and second it provides a general model which provides tremendous flexibility for optimizing buffer and bandwidth allocation to support different services. Performance of the truncated fat-banyan under uniform and bursty traffic conditions is presented.

Original languageEnglish
Pages675-680
Number of pages6
Publication statusPublished - 1 Jan 1996
EventProceedings of the 1996 IEEE International Conference on Communications, ICC'96. Part 1 (of 3) - Dallas, TX, USA
Duration: 23 Jun 199627 Jun 1996

Other

OtherProceedings of the 1996 IEEE International Conference on Communications, ICC'96. Part 1 (of 3)
CityDallas, TX, USA
Period23/6/9627/6/96

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ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Alimuddin, M., Alnuweiri, H. M., & Donaldson, R. W. (1996). Efficient design of scalable shared-memory packet switches. 675-680. Paper presented at Proceedings of the 1996 IEEE International Conference on Communications, ICC'96. Part 1 (of 3), Dallas, TX, USA, .