Digital VLSI implementation of a multi-precision neural network classifier

Amine Bermak, Dominique Martinez

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A systolic multi-precision digital VLSI classifier referred to as "SysNeuro" is presented. Unlike the usual VLSI implementation of classifiers, this hardware has been designed to achieve variable precision computations. A hardware reconfiguration is obtained by using switch elements to change the hardware connection between adjacent 4 bit neuron building blocks. With this reconfiguration concept it is possible to either increase the precision by pooling together adjacent cells or to increase the number of neurons for low levels of precision. Moreover, the design is easily programmable and can be configured to any artificial neural network (ANN) topology in order to cover various kinds of application. The chip integrates 16/8/4 neurons with a corresponding precision of 4/8/16 bits. A prototype has been successfully realized using 0.7 μm CMOS technology.

Original languageEnglish
Title of host publicationICONIP 1999, 6th International Conference on Neural Information Processing - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages560-565
Number of pages6
Volume2
ISBN (Electronic)0780358716, 9780780358713
DOIs
Publication statusPublished - 1 Jan 1999
Event6th International Conference on Neural Information Processing, ICONIP 1999 - Perth, Australia
Duration: 16 Nov 199920 Nov 1999

Other

Other6th International Conference on Neural Information Processing, ICONIP 1999
CountryAustralia
CityPerth
Period16/11/9920/11/99

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ASJC Scopus subject areas

  • Artificial Intelligence
  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Statistics, Probability and Uncertainty

Cite this

Bermak, A., & Martinez, D. (1999). Digital VLSI implementation of a multi-precision neural network classifier. In ICONIP 1999, 6th International Conference on Neural Information Processing - Proceedings (Vol. 2, pp. 560-565). [845655] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICONIP.1999.845655