Design and evaluation of scalable shared-memory ATM switches

Mohammad Alimuddin, Hussein Alnuweiri

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this w-ay, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.

Original languageEnglish
Pages (from-to)224-236
Number of pages13
JournalIEICE Transactions on Communications
VolumeE81-B
Issue number2
Publication statusPublished - 1 Jan 1998
Externally publishedYes

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Keywords

  • ATM switch
  • Bursty traffic
  • Dilation
  • LC backpressure
  • Shared-memory
  • Truncated Banyan architecture

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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