Configurable blocks for multi-precision multiplication

Oliver A. Pfänder, Reinhard Nopper, Hans Jörg Pfleiderer, Shun Zhou, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Implementing arithmetic-heavy applications such as filters or neural networks in FPGAs relies to a great extent on the realization of efficient multipliers. However, implementing high-precision multipliers only with configurable logic leads to a large lookup-table usage and considerable routing efforts. Thus, hard-wired multiplier blocks are embedded in modern FPGA devices in order to relieve the resources, but their word-length is still fixed to e.g. 18×18-bit in the Xilinx Virtex-IV DSP48 slices. In this paper, we describe our approach of creating configurable blocks suitable for multi-precision multiplication with a word-length that can be changed at runtime. We present a novel block-serial design that shows a 60% area advantage over a fully parallel multiplier and also a larger structure that can be partitioned into several fully functional smaller multipliers working simultaneously in different configurations.

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages478-481
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong
Duration: 23 Jan 200825 Jan 2008

Other

Other4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
CountryHong Kong
CityHong Kong, SAR
Period23/1/0825/1/08

Fingerprint

Field programmable gate arrays (FPGA)
Table lookup
Neural networks

Keywords

  • Embedded blocks
  • FPGA
  • Multi-precision
  • Multiplication
  • Reconfigurable multipliers

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Pfänder, O. A., Nopper, R., Pfleiderer, H. J., Zhou, S., & Bermak, A. (2008). Configurable blocks for multi-precision multiplication. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 (pp. 478-481). [4459597] https://doi.org/10.1109/DELTA.2008.109

Configurable blocks for multi-precision multiplication. / Pfänder, Oliver A.; Nopper, Reinhard; Pfleiderer, Hans Jörg; Zhou, Shun; Bermak, Amine.

Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 478-481 4459597.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pfänder, OA, Nopper, R, Pfleiderer, HJ, Zhou, S & Bermak, A 2008, Configurable blocks for multi-precision multiplication. in Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008., 4459597, pp. 478-481, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, SAR, Hong Kong, 23/1/08. https://doi.org/10.1109/DELTA.2008.109
Pfänder OA, Nopper R, Pfleiderer HJ, Zhou S, Bermak A. Configurable blocks for multi-precision multiplication. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 478-481. 4459597 https://doi.org/10.1109/DELTA.2008.109
Pfänder, Oliver A. ; Nopper, Reinhard ; Pfleiderer, Hans Jörg ; Zhou, Shun ; Bermak, Amine. / Configurable blocks for multi-precision multiplication. Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. pp. 478-481
@inproceedings{a93db4989f7d49a8bfbf2c44ab0172fa,
title = "Configurable blocks for multi-precision multiplication",
abstract = "Implementing arithmetic-heavy applications such as filters or neural networks in FPGAs relies to a great extent on the realization of efficient multipliers. However, implementing high-precision multipliers only with configurable logic leads to a large lookup-table usage and considerable routing efforts. Thus, hard-wired multiplier blocks are embedded in modern FPGA devices in order to relieve the resources, but their word-length is still fixed to e.g. 18×18-bit in the Xilinx Virtex-IV DSP48 slices. In this paper, we describe our approach of creating configurable blocks suitable for multi-precision multiplication with a word-length that can be changed at runtime. We present a novel block-serial design that shows a 60{\%} area advantage over a fully parallel multiplier and also a larger structure that can be partitioned into several fully functional smaller multipliers working simultaneously in different configurations.",
keywords = "Embedded blocks, FPGA, Multi-precision, Multiplication, Reconfigurable multipliers",
author = "Pf{\"a}nder, {Oliver A.} and Reinhard Nopper and Pfleiderer, {Hans J{\"o}rg} and Shun Zhou and Amine Bermak",
year = "2008",
doi = "10.1109/DELTA.2008.109",
language = "English",
isbn = "0769531105",
pages = "478--481",
booktitle = "Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008",

}

TY - GEN

T1 - Configurable blocks for multi-precision multiplication

AU - Pfänder, Oliver A.

AU - Nopper, Reinhard

AU - Pfleiderer, Hans Jörg

AU - Zhou, Shun

AU - Bermak, Amine

PY - 2008

Y1 - 2008

N2 - Implementing arithmetic-heavy applications such as filters or neural networks in FPGAs relies to a great extent on the realization of efficient multipliers. However, implementing high-precision multipliers only with configurable logic leads to a large lookup-table usage and considerable routing efforts. Thus, hard-wired multiplier blocks are embedded in modern FPGA devices in order to relieve the resources, but their word-length is still fixed to e.g. 18×18-bit in the Xilinx Virtex-IV DSP48 slices. In this paper, we describe our approach of creating configurable blocks suitable for multi-precision multiplication with a word-length that can be changed at runtime. We present a novel block-serial design that shows a 60% area advantage over a fully parallel multiplier and also a larger structure that can be partitioned into several fully functional smaller multipliers working simultaneously in different configurations.

AB - Implementing arithmetic-heavy applications such as filters or neural networks in FPGAs relies to a great extent on the realization of efficient multipliers. However, implementing high-precision multipliers only with configurable logic leads to a large lookup-table usage and considerable routing efforts. Thus, hard-wired multiplier blocks are embedded in modern FPGA devices in order to relieve the resources, but their word-length is still fixed to e.g. 18×18-bit in the Xilinx Virtex-IV DSP48 slices. In this paper, we describe our approach of creating configurable blocks suitable for multi-precision multiplication with a word-length that can be changed at runtime. We present a novel block-serial design that shows a 60% area advantage over a fully parallel multiplier and also a larger structure that can be partitioned into several fully functional smaller multipliers working simultaneously in different configurations.

KW - Embedded blocks

KW - FPGA

KW - Multi-precision

KW - Multiplication

KW - Reconfigurable multipliers

UR - http://www.scopus.com/inward/record.url?scp=50649092900&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50649092900&partnerID=8YFLogxK

U2 - 10.1109/DELTA.2008.109

DO - 10.1109/DELTA.2008.109

M3 - Conference contribution

SN - 0769531105

SN - 9780769531106

SP - 478

EP - 481

BT - Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

ER -