Compile-time scheduling algorithms for a heterogeneous network of workstations

Michal Cierniak, Mohammed Javeed Zaki, L. I. Wei

Research output: Contribution to journalArticle

25 Citations (Scopus)

Abstract

In this paper, we study the problem of scheduling parallel loops at compile time for a heterogeneous network of workstations. We consider heterogeneity in various aspects of parallel programming: program, processor, memory and network. A heterogeneous program has parallel loops with different amounts of work being done in each iteration; heterogeneous processors have different speeds; heterogeneous memory refers to the different amounts of user-available memory on the machines and a heterogeneous network has different communication costs between processors. We propose a simple yet comprehensive model for use in compiling for a network of processors, and develop compiler algorithms for generating optimal and near-optimal schedules of loops for load balancing, communication optimizations, network contention and memory heterogeneity. Experiments show that a significant performance improvement is achieved using our techniques.

Original languageEnglish
JournalComputer Journal
Volume40
Issue number6
Publication statusPublished - 1 Dec 1997
Externally publishedYes

Fingerprint

Computer workstations
Heterogeneous networks
Scheduling algorithms
Data storage equipment
Parallel programming
Communication
Computer networks
Resource allocation
Program processors
Scheduling
Costs
Experiments

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Information Systems
  • Software

Cite this

Compile-time scheduling algorithms for a heterogeneous network of workstations. / Cierniak, Michal; Zaki, Mohammed Javeed; Wei, L. I.

In: Computer Journal, Vol. 40, No. 6, 01.12.1997.

Research output: Contribution to journalArticle

Cierniak, Michal ; Zaki, Mohammed Javeed ; Wei, L. I. / Compile-time scheduling algorithms for a heterogeneous network of workstations. In: Computer Journal. 1997 ; Vol. 40, No. 6.
@article{6a171eae5525489aa36f05d47a93c12b,
title = "Compile-time scheduling algorithms for a heterogeneous network of workstations",
abstract = "In this paper, we study the problem of scheduling parallel loops at compile time for a heterogeneous network of workstations. We consider heterogeneity in various aspects of parallel programming: program, processor, memory and network. A heterogeneous program has parallel loops with different amounts of work being done in each iteration; heterogeneous processors have different speeds; heterogeneous memory refers to the different amounts of user-available memory on the machines and a heterogeneous network has different communication costs between processors. We propose a simple yet comprehensive model for use in compiling for a network of processors, and develop compiler algorithms for generating optimal and near-optimal schedules of loops for load balancing, communication optimizations, network contention and memory heterogeneity. Experiments show that a significant performance improvement is achieved using our techniques.",
author = "Michal Cierniak and Zaki, {Mohammed Javeed} and Wei, {L. I.}",
year = "1997",
month = "12",
day = "1",
language = "English",
volume = "40",
journal = "Computer Journal",
issn = "0010-4620",
publisher = "Oxford University Press",
number = "6",

}

TY - JOUR

T1 - Compile-time scheduling algorithms for a heterogeneous network of workstations

AU - Cierniak, Michal

AU - Zaki, Mohammed Javeed

AU - Wei, L. I.

PY - 1997/12/1

Y1 - 1997/12/1

N2 - In this paper, we study the problem of scheduling parallel loops at compile time for a heterogeneous network of workstations. We consider heterogeneity in various aspects of parallel programming: program, processor, memory and network. A heterogeneous program has parallel loops with different amounts of work being done in each iteration; heterogeneous processors have different speeds; heterogeneous memory refers to the different amounts of user-available memory on the machines and a heterogeneous network has different communication costs between processors. We propose a simple yet comprehensive model for use in compiling for a network of processors, and develop compiler algorithms for generating optimal and near-optimal schedules of loops for load balancing, communication optimizations, network contention and memory heterogeneity. Experiments show that a significant performance improvement is achieved using our techniques.

AB - In this paper, we study the problem of scheduling parallel loops at compile time for a heterogeneous network of workstations. We consider heterogeneity in various aspects of parallel programming: program, processor, memory and network. A heterogeneous program has parallel loops with different amounts of work being done in each iteration; heterogeneous processors have different speeds; heterogeneous memory refers to the different amounts of user-available memory on the machines and a heterogeneous network has different communication costs between processors. We propose a simple yet comprehensive model for use in compiling for a network of processors, and develop compiler algorithms for generating optimal and near-optimal schedules of loops for load balancing, communication optimizations, network contention and memory heterogeneity. Experiments show that a significant performance improvement is achieved using our techniques.

UR - http://www.scopus.com/inward/record.url?scp=3743155220&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=3743155220&partnerID=8YFLogxK

M3 - Article

VL - 40

JO - Computer Journal

JF - Computer Journal

SN - 0010-4620

IS - 6

ER -