Comparison of reconfigurable structures for flexible word-length multiplication

O. A. Pfänder, R. Nopper, H. J. Pfleiderer, S. Zhou, Amine Bermak

Research output: Contribution to journalArticle

2 Citations (Scopus)


Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

Original languageEnglish
Pages (from-to)113-118
Number of pages6
JournalAdvances in Radio Science
Publication statusPublished - 2008
Externally publishedYes


ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Pfänder, O. A., Nopper, R., Pfleiderer, H. J., Zhou, S., & Bermak, A. (2008). Comparison of reconfigurable structures for flexible word-length multiplication. Advances in Radio Science, 6, 113-118.