### Abstract

Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

Original language | English |
---|---|

Pages (from-to) | 113-118 |

Number of pages | 6 |

Journal | Advances in Radio Science |

Volume | 6 |

Publication status | Published - 2008 |

Externally published | Yes |

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### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*Advances in Radio Science*,

*6*, 113-118.

**Comparison of reconfigurable structures for flexible word-length multiplication.** / Pfänder, O. A.; Nopper, R.; Pfleiderer, H. J.; Zhou, S.; Bermak, Amine.

Research output: Contribution to journal › Article

*Advances in Radio Science*, vol. 6, pp. 113-118.

}

TY - JOUR

T1 - Comparison of reconfigurable structures for flexible word-length multiplication

AU - Pfänder, O. A.

AU - Nopper, R.

AU - Pfleiderer, H. J.

AU - Zhou, S.

AU - Bermak, Amine

PY - 2008

Y1 - 2008

N2 - Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

AB - Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

UR - http://www.scopus.com/inward/record.url?scp=67749149017&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67749149017&partnerID=8YFLogxK

M3 - Article

VL - 6

SP - 113

EP - 118

JO - Advances in Radio Science

JF - Advances in Radio Science

SN - 1684-9965

ER -