A CMOS on-chip ID generation scheme is proposed. Using the antenna effect during the chip fabrication, one gate in a transistor pair is physically randomly broken down due to the process variation and an on-chip ID number is thus created depending on its polarity. The generated ID not only is permanently immune from environment changes such as supply voltage and temperature, but also consumes ultra-low leakage power without any dynamic transitions. The functionality of the proposed ID generation scheme has been experimentally verified by a fabricated chip in 0.18 μm CMOS process.
- antenna effect
- CMOS on-chip ID
- true random
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering