ATLAS I: A single-chip, gigabit ATM switch with HIC/HS links and multi-lane back-pressure

M. Katevenis, D. N. Serpanos, G. Dimitriadis

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

ATLAS I is a single-chip ATM switch that uses IEEE Std. 1355 'HIC' gigabit links and implements optional credit-based flow control. It is a 16 × 16 switch with 20 Gb s-1 aggregate I/O throughput, three priority levels, 256-cell shared buffer, and 54 output queues achieving submicrosecond cut-through latency; furthermore, it supports rate-based flow control, link bundling, multicasting, and load monitoring. ATLAS I is targeted at use in interconnections ranging from wide area (WAN) to LAN and desktop (DAN) networking, and supports a mixture of services from real-time, guaranteed quality-of-service to best-effort, bursty amd flooding traffic. Target applications range from telecom to multimedia and multiprocessor NOWs. ATLAS I implements a multi-lane back-pressure (credit) flow control scheme, which in conjunction with shared buffering provides high performance and robust operation, since it eliminates the head-of-line blocking problems of input queuing and single-lane back-pressure. We present the queue model of the switch, we describe how multi-lane back-pressure is added on top of single-lane 1355 standard links, as an optional extension, and we show how the link interfaces are implemented and how their parameters are evaluated.

Original languageEnglish
Pages (from-to)481-490
Number of pages10
JournalMicroprocessors and Microsystems
Volume21
Issue number7-8
DOIs
Publication statusPublished - 30 Mar 1998

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Keywords

  • ATM
  • Credit-based flow control
  • High-speed switching
  • IEEE 1355
  • Multi-lane back-pressure

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

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