ASIP-controlled inverse integer transform for H.264/AVC compression

N. T. Ngo, T. T.T. Do, T. M. Le, Y. S. Kadam, A. Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4×4 and 8×8 inverse integer transform with additional support for 2×2 and 4×4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4×4 circuit in the 8×8 circuit, while achieving a speed of 176MHz.

Original languageEnglish
Title of host publicationProceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008
Pages158-164
Number of pages7
DOIs
Publication statusPublished - 17 Sep 2008
Event19th IEEE/IFIP International Symposium on Rapid System Prototyping, RSP 2008 - Monterey, CA, United States
Duration: 2 Jun 20085 Jun 2008

Publication series

NameProceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008

Other

Other19th IEEE/IFIP International Symposium on Rapid System Prototyping, RSP 2008
CountryUnited States
CityMonterey, CA
Period2/6/085/6/08

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ASJC Scopus subject areas

  • Software
  • Control and Systems Engineering

Cite this

Ngo, N. T., Do, T. T. T., Le, T. M., Kadam, Y. S., & Bermak, A. (2008). ASIP-controlled inverse integer transform for H.264/AVC compression. In Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008 (pp. 158-164). [4550902] (Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008). https://doi.org/10.1109/RSP.2008.34