Abstract
In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4×4 and 8×8 inverse integer transform with additional support for 2×2 and 4×4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4×4 circuit in the 8×8 circuit, while achieving a speed of 176MHz.
| Original language | English |
|---|---|
| Title of host publication | Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008 |
| Pages | 158-164 |
| Number of pages | 7 |
| DOIs | |
| Publication status | Published - 2008 |
| Externally published | Yes |
| Event | 19th IEEE/IFIP International Symposium on Rapid System Prototyping, RSP 2008 - Monterey, CA, United States Duration: 2 Jun 2008 → 5 Jun 2008 |
Other
| Other | 19th IEEE/IFIP International Symposium on Rapid System Prototyping, RSP 2008 |
|---|---|
| Country | United States |
| City | Monterey, CA |
| Period | 2/6/08 → 5/6/08 |
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ASJC Scopus subject areas
- Software
- Control and Systems Engineering
Cite this
ASIP-controlled inverse integer transform for H.264/AVC compression. / Ngo, N. T.; Do, T. T T; Le, T. M.; Kadam, Y. S.; Bermak, Amine.
Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008. 2008. p. 158-164 4550902.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - ASIP-controlled inverse integer transform for H.264/AVC compression
AU - Ngo, N. T.
AU - Do, T. T T
AU - Le, T. M.
AU - Kadam, Y. S.
AU - Bermak, Amine
PY - 2008
Y1 - 2008
N2 - In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4×4 and 8×8 inverse integer transform with additional support for 2×2 and 4×4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4×4 circuit in the 8×8 circuit, while achieving a speed of 176MHz.
AB - In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4×4 and 8×8 inverse integer transform with additional support for 2×2 and 4×4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4×4 circuit in the 8×8 circuit, while achieving a speed of 176MHz.
UR - http://www.scopus.com/inward/record.url?scp=51549119132&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51549119132&partnerID=8YFLogxK
U2 - 10.1109/RSP.2008.34
DO - 10.1109/RSP.2008.34
M3 - Conference contribution
AN - SCOPUS:51549119132
SN - 9780769531809
SP - 158
EP - 164
BT - Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008
ER -