Architecture of three dimensional compressive acquisition CMOS image sensor

Milin Zhang, Panpan Xu, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, architecture of a three dimensional (3D) compressive acquisition CMOS image sensor integrated with on-line parallel compression algorithm is proposed. The proposed 3D sensor architecture consists of three hierarchy layers: an image acquisition hierarchy, an image compression hierarchy layer, and an image storage hierarchy layer. The image acquisition hierarchy converts light intensity into current using photodiode. In the second layer, the analog current values are converted into time-slot by comparing with a reference voltage value. The time-slot signal is used in the on-line compression processing. The digital brightest pixel value is used as a reference value, while the differential value between the reference and the raw pixel value is calculated and quantized. The quantized results (typically 2-bit) as well as the reference brightest pixel value are stored in the third hierarchy layer. Compared with standard two dimensional (2D) compressive acquisition CMOS image sensor design, about 70% silicon area is reduced by the 3D integration of different layers. In addition, the increase of the fill factor can be expected as high as near 100%.

Original languageEnglish
Title of host publicationIEEE Sensors 2010 Conference, SENSORS 2010
Pages114-117
Number of pages4
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event9th IEEE Sensors Conference 2010, SENSORS 2010 - Waikoloa, HI, United States
Duration: 1 Nov 20104 Nov 2010

Other

Other9th IEEE Sensors Conference 2010, SENSORS 2010
CountryUnited States
CityWaikoloa, HI
Period1/11/104/11/10

Fingerprint

Image sensors
Image acquisition
Pixels
Image compression
Photodiodes
Silicon
Sensors
Electric potential
Processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Zhang, M., Xu, P., & Bermak, A. (2010). Architecture of three dimensional compressive acquisition CMOS image sensor. In IEEE Sensors 2010 Conference, SENSORS 2010 (pp. 114-117). [5690661] https://doi.org/10.1109/ICSENS.2010.5690661

Architecture of three dimensional compressive acquisition CMOS image sensor. / Zhang, Milin; Xu, Panpan; Bermak, Amine.

IEEE Sensors 2010 Conference, SENSORS 2010. 2010. p. 114-117 5690661.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, M, Xu, P & Bermak, A 2010, Architecture of three dimensional compressive acquisition CMOS image sensor. in IEEE Sensors 2010 Conference, SENSORS 2010., 5690661, pp. 114-117, 9th IEEE Sensors Conference 2010, SENSORS 2010, Waikoloa, HI, United States, 1/11/10. https://doi.org/10.1109/ICSENS.2010.5690661
Zhang M, Xu P, Bermak A. Architecture of three dimensional compressive acquisition CMOS image sensor. In IEEE Sensors 2010 Conference, SENSORS 2010. 2010. p. 114-117. 5690661 https://doi.org/10.1109/ICSENS.2010.5690661
Zhang, Milin ; Xu, Panpan ; Bermak, Amine. / Architecture of three dimensional compressive acquisition CMOS image sensor. IEEE Sensors 2010 Conference, SENSORS 2010. 2010. pp. 114-117
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