Architecture of a low storage digital pixel sensor array with an on-line block-based compression

Milin Zhang, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30dB with a compression ratio of less than 3BPP.

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages167-170
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong
Duration: 23 Jan 200825 Jan 2008

Other

Other4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
CountryHong Kong
CityHong Kong, SAR
Period23/1/0825/1/08

Fingerprint

Digital storage
Sensor arrays
Pixels
Data storage equipment
Processing

Keywords

  • Block-based compression
  • DPS
  • Error propagation
  • Low storage

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Zhang, M., & Bermak, A. (2008). Architecture of a low storage digital pixel sensor array with an on-line block-based compression. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 (pp. 167-170). [4459533] https://doi.org/10.1109/DELTA.2008.117

Architecture of a low storage digital pixel sensor array with an on-line block-based compression. / Zhang, Milin; Bermak, Amine.

Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 167-170 4459533.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, M & Bermak, A 2008, Architecture of a low storage digital pixel sensor array with an on-line block-based compression. in Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008., 4459533, pp. 167-170, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, SAR, Hong Kong, 23/1/08. https://doi.org/10.1109/DELTA.2008.117
Zhang M, Bermak A. Architecture of a low storage digital pixel sensor array with an on-line block-based compression. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 167-170. 4459533 https://doi.org/10.1109/DELTA.2008.117
Zhang, Milin ; Bermak, Amine. / Architecture of a low storage digital pixel sensor array with an on-line block-based compression. Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. pp. 167-170
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