Arbitrated time-to-first spike CMOS image sensor with on-chip histogram equalization

Shoushun Chen, Amine Bermak

Research output: Contribution to journalArticle

60 Citations (Scopus)

Abstract

This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (HE). The pixel values are read-out using an asynchronous handshaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1 × 0.6 mm2). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in AMIS 0.35 μm process with a silicon area of 3.1 × 3.2 mm2. Successful operation of the prototype is illustrated through experimental measurements.

Original languageEnglish
Pages (from-to)346-357
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume15
Issue number3
DOIs
Publication statusPublished - Mar 2007
Externally publishedYes

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Image sensors
Pixels
Silicon
Computer hardware description languages
Simulators
Switches
Processing

Keywords

  • Address event representation (AER)
  • CMOS image sensors
  • On-chip histogram equalization
  • Time-to-first spike (TFS) vision sensor

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Arbitrated time-to-first spike CMOS image sensor with on-chip histogram equalization. / Chen, Shoushun; Bermak, Amine.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 3, 03.2007, p. 346-357.

Research output: Contribution to journalArticle

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