An extensible memory simulation framework for chip multi-processors

Mingliang Liu, Lin Qiao, Yu Chen, Fucen Zeng, Chao Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

As the Chip Multi-processors (CMPs) becoming more attractive for high performance computing, key design decisions especially concerning memory hierarchy should be made more carefully. However, the existing micro-architecture simulators and software tools merely meet the needs of on-chip memory performance modeling. This paper presents a new pin-tool-based memory simulation framework for CMP, called gsim, which is intrinsically extensible with perfect support for widely used x86 ISA. The gsim is time-efficient with ignorable accuracy loss and can be easily extended for memory behavior evaluation and onchip design space exploration.

Original languageEnglish
Title of host publicationProceedings - 2009 International Conference on Computational Intelligence and Software Engineering, CiSE 2009
DOIs
Publication statusPublished - 1 Dec 2009
Event2009 International Conference on Computational Intelligence and Software Engineering, CiSE 2009 - Wuhan
Duration: 11 Dec 200913 Dec 2009

Other

Other2009 International Conference on Computational Intelligence and Software Engineering, CiSE 2009
CityWuhan
Period11/12/0913/12/09

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Keywords

  • Architecture simulator
  • Cache memory
  • Chip multiprocessors
  • Software modeling

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computational Theory and Mathematics
  • Software

Cite this

Liu, M., Qiao, L., Chen, Y., Zeng, F., & Zhang, C. (2009). An extensible memory simulation framework for chip multi-processors. In Proceedings - 2009 International Conference on Computational Intelligence and Software Engineering, CiSE 2009 [5363443] https://doi.org/10.1109/CISE.2009.5363443